| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 139 case AArch64::Q22: in isOdd()
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| D | AArch64SchedPredicates.td | 192 CheckRegOperand<0, Q22>,
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| D | AArch64RegisterInfo.td | 410 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
771 def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 139 case AArch64::Q22: in isOdd()
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| D | AArch64SchedPredicates.td | 192 CheckRegOperand<0, Q22>,
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| D | AArch64RegisterInfo.td | 413 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
791 def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 140 case AArch64::Q22: in isOdd()
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| D | AArch64RegisterInfo.td | 377 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
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| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 221 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, in initLLVMToCVRegMapping()
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| D | AArch64InstPrinter.cpp | 1200 case AArch64::Q21: Reg = AArch64::Q22; break; in getNextVectorRegister()
1201 case AArch64::Q22: Reg = AArch64::Q23; break; in getNextVectorRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 217 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, in initLLVMToCVRegMapping()
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| D | AArch64InstPrinter.cpp | 1186 case AArch64::Q21: Reg = AArch64::Q22; break; in getNextVectorRegister()
1187 case AArch64::Q22: Reg = AArch64::Q23; break; in getNextVectorRegister()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1249 case AArch64::Q21: Reg = AArch64::Q22; break; in getNextVectorRegister()
1250 case AArch64::Q22: Reg = AArch64::Q23; break; in getNextVectorRegister()
|
| /external/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| D | VEDisassembler.cpp | 95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
440 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 309 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
633 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 312 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
636 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| D | VEAsmParser.cpp | 125 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
|
| /external/ImageMagick/MagickCore/ |
| D | enhance.c | 409 const size_t *Q22,const size_t *Q11,const size_t *Q21, in InterpolateCLAHE() argument
431 Q22[intensity])+(tile->height-y)*((double) x*Q11[intensity]+ in InterpolateCLAHE()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 163 Q22 = 143,
2660 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
3924 { AArch64::Q22, 86U },
4203 { AArch64::Q22, 86U },
20418 …ch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, 0 };
20420 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
20422 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
20424 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
20446 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
20448 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
[all …]
|
| D | AArch64GenSubtargetInfo.inc | 14037 || MI->getOperand(0).getReg() == AArch64::Q22
14191 || MI->getOperand(0).getReg() == AArch64::Q22
14345 || MI->getOperand(0).getReg() == AArch64::Q22
14556 || MI->getOperand(0).getReg() == AArch64::Q22
14597 || MI->getOperand(0).getReg() == AArch64::Q22
16566 || MI->getOperand(0).getReg() == AArch64::Q22
16607 || MI->getOperand(0).getReg() == AArch64::Q22
19673 || MI->getOperand(0).getReg() == AArch64::Q22
19827 || MI->getOperand(0).getReg() == AArch64::Q22
19981 || MI->getOperand(0).getReg() == AArch64::Q22
[all …]
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| D | AArch64GenAsmMatcher.inc | 11447 case AArch64::Q22: OpKind = MCK_FPR128; break;
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1879 .Case("v22", AArch64::Q22) in matchVectorRegName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2112 .Case("v22", AArch64::Q22) in MatchNeonVectorRegName()
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2157 .Case("v22", AArch64::Q22) in MatchNeonVectorRegName()
|