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Searched refs:QPU_GET_FIELD (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.c36 assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP || in set_src_raddr()
37 QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr); in set_src_raddr()
42 assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP || in set_src_raddr()
43 QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) && in set_src_raddr()
44 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM); in set_src_raddr()
49 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) { in set_src_raddr()
50 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr); in set_src_raddr()
53 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP); in set_src_raddr()
288 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD); in qpu_num_sf_accesses()
289 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL); in qpu_num_sf_accesses()
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Dvc4_qpu_validate.c41 return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w || in writes_reg()
42 QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w); in writes_reg()
51 { QPU_GET_FIELD(inst, QPU_ADD_A) }, in _reads_reg()
52 { QPU_GET_FIELD(inst, QPU_ADD_B) }, in _reads_reg()
53 { QPU_GET_FIELD(inst, QPU_MUL_A) }, in _reads_reg()
54 { QPU_GET_FIELD(inst, QPU_MUL_B) }, in _reads_reg()
60 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) in _reads_reg()
64 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM) in _reads_reg()
70 (QPU_GET_FIELD(inst, QPU_RADDR_A) == r)) in _reads_reg()
74 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM && in _reads_reg()
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Dvc4_qpu_disasm.c300 QPU_GET_FIELD(inst, QPU_WADDR_MUL) : in print_alu_dst()
301 QPU_GET_FIELD(inst, QPU_WADDR_ADD)); in print_alu_dst()
303 uint32_t pack = QPU_GET_FIELD(inst, QPU_PACK); in print_alu_dst()
325 QPU_GET_FIELD(inst, QPU_RADDR_A) : in print_alu_src()
326 QPU_GET_FIELD(inst, QPU_RADDR_B)); in print_alu_src()
327 uint32_t unpack = QPU_GET_FIELD(inst, QPU_UNPACK); in print_alu_src()
328 bool has_si = QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM; in print_alu_src()
329 uint32_t si = QPU_GET_FIELD(inst, QPU_SMALL_IMM); in print_alu_src()
364 uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD); in print_add_op()
365 uint32_t cond = QPU_GET_FIELD(inst, QPU_COND_ADD); in print_add_op()
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Dvc4_qpu_schedule.c135 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); in qpu_writes_r4()
206 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM) in reads_uniform()
209 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF || in reads_uniform()
210 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF && in reads_uniform()
211 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) || in reads_uniform()
212 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) || in reads_uniform()
213 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL))); in reads_uniform()
326 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD); in calculate_deps()
327 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL); in calculate_deps()
328 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD); in calculate_deps()
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Dvc4_qpu_emit.c209 ASSERTED uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK); in set_last_dst_pack()
621 assert(QPU_GET_FIELD(*c->last_thrsw, QPU_SIG) == in vc4_generate_code()
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
636 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
638 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
644 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
646 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
658 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], in vc4_generate_code()
Dvc4_qpu_defines.h238 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate_shaders.c115 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); in raddr_add_a_to_live_reg_index()
116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in raddr_add_a_to_live_reg_index()
117 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); in raddr_add_a_to_live_reg_index()
118 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in raddr_add_a_to_live_reg_index()
185 QPU_GET_FIELD(inst, QPU_WADDR_MUL) : in check_tmu_write()
186 QPU_GET_FIELD(inst, QPU_WADDR_ADD)); in check_tmu_write()
187 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); in check_tmu_write()
188 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in check_tmu_write()
192 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); in check_tmu_write()
195 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B); in check_tmu_write()
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/external/mesa3d/src/broadcom/qpu/
Dqpu_pack.c41 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro
719 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_ADD); in v3d_qpu_add_unpack()
720 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A); in v3d_qpu_add_unpack()
721 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_B); in v3d_qpu_add_unpack()
722 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A); in v3d_qpu_add_unpack()
846 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A); in v3d_qpu_add_unpack()
873 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_MUL); in v3d_qpu_mul_unpack()
874 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A); in v3d_qpu_mul_unpack()
875 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_B); in v3d_qpu_mul_unpack()
935 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M); in v3d_qpu_mul_unpack()
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/external/libdrm/vc4/
Dvc4_qpu_defines.h218 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) macro