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Searched refs:QPU_W_ACC0 (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu_schedule.c246 case QPU_W_ACC0: in process_waddr_deps()
251 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0], in process_waddr_deps()
494 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 || in reads_too_soon_after_write()
495 scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 || in reads_too_soon_after_write()
496 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 || in reads_too_soon_after_write()
497 scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) { in reads_too_soon_after_write()
Dvc4_qpu_validate.c310 if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) || in vc4_qpu_validate()
311 writes_reg(insts[i - 1], QPU_W_ACC0 + mux_b)) { in vc4_qpu_validate()
Dvc4_qpu_defines.h85 QPU_W_ACC0 = 32, /* aka r0 */ enumerator
Dvc4_qpu_disasm.c163 [QPU_W_ACC0] = "r0",
Dvc4_qpu.c322 case QPU_W_ACC0: in qpu_waddr_ignores_ws()
/external/libdrm/vc4/
Dvc4_qpu_defines.h82 QPU_W_ACC0 = 32, /* aka r0 */ enumerator
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate_shaders.c106 return 64 + waddr - QPU_W_ACC0; in waddr_to_live_reg_index()