/external/libxaac/decoder/armv7/ |
D | ixheaacd_rescale_subbandsamples.s | 38 LDR R10, [R9], #4 55 ADD R10, R10, R2, LSL #2 59 LDR R11, [R10] 61 LDRGE R5, [R10, #4] 64 STR R11, [R10], #4 67 STRGE R5, [R10], #4 71 LDR R10, [R9], #4 81 ADD R10, R10, R2, LSL #2 84 LDR R11, [R10] 86 LDRGE R5, [R10, #4] [all …]
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D | ixheaacd_apply_rot.s | 38 ADD R10, R7, R8 39 STRH R10, [R11, #-96] 48 ADD R10, R7, R8 49 STRH R10, [R11], #4 57 ADD R10, R7, R8 58 STRH R10, [R11, #-96] 68 ADD R10, R7, R8 69 STRH R10, [R11], #4 86 SMULWB R10, R6, R8 89 QADD R5, R9, R10 [all …]
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D | ixheaacd_tns_parcor2lpc_32x16.s | 43 MOV R10, R9, ASR R8 48 MOV R11, R10 55 QADD R14, R10, R5 60 QADD R10, R10, R2 62 MOVS R2, R10 99 QADD R2, R10, R5 104 MOV R10, #0 111 SUBS R10, R6, #1
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D | ixheaacd_sbr_qmfanal32_winadds_eld.s | 66 MOV R10, R2 @ 78 SUB R10, R10, #8 107 MOV R2, R10 @ 109 MOV R10, R3 118 SUB R10, R10, #8 139 MOV R3, R10 151 MOV R10, R2 169 SUB R10, R10, #8 196 MOV R2, R10 205 MOV R10, R3 [all …]
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D | ixheaacd_overlap_add2.s | 47 ADD R10, R0, R9 49 VLD2.16 {D0, D1}, [R10]! 65 VLD2.16 {D8, D9}, [R10]! 79 VLD2.16 {D0, D1}, [R10]! 100 VLD2.16 {D8, D9}, [R10]! 134 MOV R10, R5, LSL #1 147 SUB R11, R10, #1 148 MOV R10, R11, LSL #2 149 ADD R10, R0, R10 151 SUB R10, R10, R12 [all …]
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D | ixheaacd_post_twiddle_overlap.s | 62 LDR R10, [R2], #4 64 SMULWT R11, R8, R10 65 SMULWB R12, R9, R10 66 SMULWB R5, R8, R10 67 SMLAWT R7, R9, R10, R5 74 SMULWB R10, R5, R9 77 ADD R8, R8, R10 81 LDR R10, [R6], #-32 84 SMULWB R7, R8, R10 87 SMULWT R12, R8, R10 [all …]
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D | ixheaacd_esbr_cos_sin_mod_loop2.s | 34 ADD R10, R0, #256 35 ADD R11, R10, R2, LSL #3 58 LDR R6, [R10] 65 LDR R6, [R10, #4] 67 STR R6, [R10], #4 91 VST1.32 {D12[1]}, [R10]! 97 VLD1.32 {D3}, [R10] 120 VST1.32 {D16[1]}, [R10]! 150 VST1.32 {D12[1]}, [R10]!
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D | ixheaacd_cos_sin_mod.s | 51 SUB R10, SP, #516 54 AND R12, R10, #7 56 ADDNE R10, R10, #4 72 ADD R11, R10, R6 106 STR R12, [R10, #4] 107 STR R14, [R10], #8 122 STR R12, [R10, #0xF8] 123 STR R14, [R10, #0xFC] 168 STR R12, [R10, #4] 169 STR R14, [R10], #8 [all …]
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D | ixheaacd_sbr_qmfsyn64_winadd.s | 42 MOV R10, R0 83 MOV R0, R10 90 MOV R10, R1 122 MOV R1, R10 124 MOV R10, R0 153 MOV R0, R10 159 MOV R10, R1 180 MOV R1, R10 197 MOV R10, R0 245 MOV R0, R10 [all …]
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D | ixheaacd_esbr_qmfsyn64_winadd.s | 31 MOV R10, R0 79 MOV R0, R10 84 MOV R10, R1 132 MOV R1, R10 134 MOV R10, R0 172 MOV R0, R10 177 MOV R10, R1 222 MOV R1, R10 224 MOV R10, R0 261 MOV R0, R10 [all …]
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D | ixheaacd_sbr_qmfanal32_winadds.s | 88 MOV R10, R2 128 MOV R2, R10 130 MOV R10, R3 158 MOV R3, R10 170 MOV R10, R2 214 MOV R2, R10 223 MOV R10, R3 250 MOV R3, R10
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D | ixheaacd_overlap_add1.s | 35 MOV R10, R5, LSL #1 36 SUB R11, R10, #1 37 MOV R10, R11, LSL #2 38 ADD R10, R0, R10 39 SUB R10, R10, #12 47 VLD1.32 {D6, D7}, [R10], R12 96 VLD1.32 {D6, D7}, [R10], R12 140 VLD1.32 {D6, D7}, [R10], R12 210 VLD1.32 {D6, D7}, [R10], R12
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D | ixheaacd_conv_ergtoamplitude.s | 32 MOVW R10, #0x5A82 55 SMULWBNE R12, R12, R10 82 SMULWBNE R8, R8, R10 110 SMULWBNE R8, R8, R10
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D | ixheaacd_conv_ergtoamplitudelp.s | 32 MOVW R10, #0x1FF 48 AND R6, R6, R10 74 AND R6, R6, R10 102 ANDS R6, R6, R10
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/external/libhevc/decoder/arm/ |
D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 117 MOVW R10,#0x3311 118 VMOV.16 D0[0],R10 @//C1 120 MOVW R10,#0xF379 121 VMOV.16 D0[1],R10 @//C2 123 MOVW R10,#0xE5F8 124 VMOV.16 D0[2],R10 @//C3 126 MOVW R10,#0x4092 127 VMOV.16 D0[3],R10 @//C4 130 MOV R10,#128 131 VDUP.8 D1,R10 [all …]
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/external/llvm-project/llvm/test/CodeGen/Hexagon/ |
D | fmul-v67.ll | 13 ; CHECK-DAG: [[R10:(r[0-9]+:[0-9]+)]] = dfmpyfix(r1:0,r3:2) 15 ; CHECK: [[R12:(r[0-9]+:[0-9]+)]] = dfmpyll([[R10]],[[R11]]) 16 ; CHECK: [[R12]] += dfmpylh([[R10]],[[R11]]) 17 ; CHECK: [[R12]] += dfmpylh([[R11]],[[R10]]) 18 ; CHECK: [[R12]] += dfmpyhh([[R10]],[[R11]])
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/external/llvm/test/CodeGen/Mips/ |
D | atomic.ll | 145 ; O0: ld $[[R10:[0-9]+]] 146 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) 190 ; O0: ld $[[R10:[0-9]+]] 191 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) 235 ; O0: ld $[[R10:[0-9]+]] 236 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) 281 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 283 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] [all …]
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/external/llvm/lib/Target/MSP430/ |
D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs() 49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs() 54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs() 60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
D | MSP430RegisterInfo.cpp | 43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs() 48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs() 53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs() 59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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/external/llvm-project/llvm/lib/Target/MSP430/ |
D | MSP430RegisterInfo.cpp | 43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs() 48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs() 53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs() 59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
D | XCoreRegisterInfo.td | 35 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 48 R4, R5, R6, R7, R8, R9, R10, 55 R4, R5, R6, R7, R8, R9, R10,
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/external/llvm-project/llvm/lib/Target/XCore/ |
D | XCoreRegisterInfo.td | 35 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 48 R4, R5, R6, R7, R8, R9, R10, 55 R4, R5, R6, R7, R8, R9, R10,
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/external/llvm/lib/Target/XCore/ |
D | XCoreRegisterInfo.td | 36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 49 R4, R5, R6, R7, R8, R9, R10, 56 R4, R5, R6, R7, R8, R9, R10,
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/external/llvm/lib/Target/Lanai/ |
D | LanaiRegisterInfo.td | 36 def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>; 51 R10, RR1, R11, RR2, // programmer controlled registers
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
D | LanaiRegisterInfo.td | 35 def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>; 50 R10, RR1, R11, RR2, // programmer controlled registers
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