| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_apply_rot.s | 30 ADD R11, R0, R5
32 LDRSH R5, [R11, #-98]
33 LDRSH R6, [R11, #94]
34 LDRSH R7, [R11, #-96]
35 LDRSH R8, [R11, #96]
37 STRH R9, [R11, #-98]
39 STRH R10, [R11, #-96]
42 LDRSH R5, [R11, #-2]
43 LDRSH R6, [R11, #190]
44 LDRSH R7, [R11]
[all …]
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| D | ixheaacd_rescale_subbandsamples.s | 26 STMFD SP!, {R4-R11, R14}
59 LDR R11, [R10]
63 MOV R11, R11, LSL R4
64 STR R11, [R10], #4
84 LDR R11, [R10]
88 MOV R11, R11, ASR R4
89 STR R11, [R10], #4
117 LDR R11, [R10]
119 MOV R11, R11, LSL R4
121 STR R11, [R10], #4
[all …]
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| D | ixheaacd_conv_ergtoamplitude.s | 45 MOV R11, R6, LSL R8
47 MOV R11, R11, ASR #5
48 ANDS R11, R11, R14
50 BIC R11, R11, #1
51 LDRH R12, [R11, R5]
73 MOV R11, R6, LSL R8
74 MOV R11, R11, ASR #5
75 ANDS R11, R11, R14
77 BIC R11, R11, #1
78 LDRH R8, [R11, R5]
[all …]
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| D | ixheaacd_enery_calc_per_subband.s | 77 MOVS R11, R2
87 SUBS R11, R11, #2
97 MOV R11, R2
103 SUBS R11, R11, #2
118 SUBS R11, R11, #2
136 SMULBB R11, R4, R9
139 MOV R11, R11, ASR #15
140 CMP R11, #0x00008000
141 MVNEQ R11, R11
142 STRH R11, [R7], #2
[all …]
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| D | ixheaacd_overlap_add2.s | 50 MOV R11, R6, LSL #2
89 VST1.32 {D24[0]}, [R2], R11
91 VST1.32 {D24[1]}, [R2], R11
93 VST1.32 {D25[0]}, [R2], R11
96 VST1.32 {D25[1]}, [R2], R11
109 VST1.32 D16[0], [R2], R11
115 VST1.32 D16[1], [R2], R11
116 VST1.32 D17[0], [R2], R11
117 VST1.32 D17[1], [R2], R11
123 VST1.32 D24[0], [R2], R11
[all …]
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| D | ixheaacd_overlap_add1.s | 36 SUB R11, R10, #1
37 MOV R10, R11, LSL #2
40 MOV R8, R11, LSL #1
54 SUB R11, R5, #1
56 SMULBB R11, R11, R6
57 MOV R11, R11, LSL #1
59 ADD R11, R11, R2
124 VST1.16 D26[0], [R11], R4
126 VST1.16 D26[1], [R11], R4
128 VST1.16 D26[2], [R11], R4
[all …]
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| D | ixheaacd_cos_sin_mod.s | 72 ADD R11, R10, R6
137 STR R12, [R11, #-4]
138 STR R3, [R11], #-8
153 STR R3, [R11, #0x108]
154 STR R14, [R11, #0x104]
196 STR R3, [R11], #-4
197 STR R12, [R11], #-4
213 STR R3, [R11, #0x104]
214 STR R12, [R11, #0x108]
279 LDR R11, [R8, #4]
[all …]
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| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 35 ADD R11, R10, R2, LSL #3
36 SUB R11, R11, #4
56 VLD1.32 {D2[1]}, [R11] @re = *psubband12;
63 STR R7, [R11], #-4
69 VLD1.32 {D3[1]}, [R11]
93 VST1.32 {D16[1]}, [R11], R8
99 LDR R6, [R11] @RE3
119 VST1.32 {D12[1]}, [R11], R8
129 VLD1.32 {D2[1]}, [R11]
151 VST1.32 {D16[1]}, [R11], R8
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| D | ixheaacd_post_twiddle_overlap.s | 64 SMULWT R11, R8, R10
68 SUB R8, R12, R11
75 SMULWB R11, R8, R12
78 ADD R5, R5, R11
80 LDR R11, [sp, #104]
89 CMP R11, #0
92 RSBS R9, R11, #16
101 RSBS R9, R11, #31
106 MOVEQ R7, R7, LSL R11
108 RSBS R9, R11, #31
[all …]
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| D | ixheaacd_sbr_qmfsyn64_winadd.s | 43 MOV R11, R2
86 MOV R2, R11
96 MOV R11, R12
120 MOV R12, R11
130 MOV R11, R2
156 MOV R2, R11
164 MOV R11, R12
182 MOV R12, R11
207 MOV R11, R2
243 MOV R2, R11
[all …]
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| D | ixheaacd_tns_parcor2lpc_32x16.s | 48 MOV R11, R10
98 QADD R11, R11, R5
100 MOV R11, R11, ASR #16
102 STRH R11, [R4]
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| D | ixheaacd_esbr_qmfsyn64_winadd.s | 32 MOV R11, R2
82 MOV R2, R11
87 MOV R11, R12
131 MOV R12, R11
138 MOV R11, R2
175 MOV R2, R11
180 MOV R11, R12
221 MOV R12, R11
233 MOV R11, R2
264 MOV R2, R11
[all …]
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| D | ixheaacd_tns_ar_filter_fixed.s | 152 @VMOV R11,D6[0]
154 LDR R11, [SP]
192 @VMOV R11,D6[0]
194 LDR R11, [SP]
237 @VMOV R11,D6[0]
239 LDR R11, [SP]
284 @VMOV R11,D6[0]
286 LDR R11, [SP]
334 @VMOV R11,D6[0]
336 LDR R11, [SP]
[all …]
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| D | ixheaacd_dct3_32.s | 45 MOV R11, #-4
134 VLD1.32 {Q1}, [R7], R11
150 VLD1.32 {Q4}, [R5], R11
182 VLD1.32 D2[0], [R7], R11
185 VLD1.32 D2[1], [R7], R11
189 VLD1.32 D3[0], [R7], R11
199 VLD1.32 D8[0], [R5], R11
206 VLD1.32 D8[1], [R5], R11
211 VLD1.32 D9[0], [R5], R11
231 VLD1.32 D2[0], [R7], R11
[all …]
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| D | ixheaacd_conv_ergtoamplitudelp.s | 31 MOVW R11, #0x5A82
55 SMULWBNE R12, R12, R11
81 SMULWBNE R8, R8, R11
109 SMULWBNE R8, R8, R11
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| D | ixheaacd_sbr_qmfanal32_winadds.s | 81 MOV R11, R4
83 ADD R11, R11, #128
187 VST1.32 {Q15}, [R11]!
262 VST1.32 {Q15}, [R11]!
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| D | ixheaacd_sbr_qmfanal32_winadds_eld.s | 61 MOV R11, R4 @ Mov winAdd to R11
63 ADD R11, R11, #128 @ increment winAdd by 128
168 VST1.32 {Q15}, [R11]!
245 VST1.32 {Q15}, [R11]!
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 155 @R11 tmp register
242 ADD R11,R9,R12,LSL #2 @Load address of g_ai2_ihevc_trans_32[4]
246 VLD1.S16 D24,[R11],R12 @ LOAD g_ai2_ihevc_trans_32[4][0-4]
283 …VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_32[12][0-4] -- 1st cycle dual issue with p…
298 VLD1.S16 D26,[R11],R12 @LOAD g_ai2_ihevc_trans_32[20][0-4]
308 VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_32[28][0-4]
322 ADD R11,R9,R12,LSL #1 @Load address of g_ai2_ihevc_trans_32[2]
324 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[2][0-7]
346 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[6][0-7]
356 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[10][0-7] -- dual issue with prev. MLAL
[all …]
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | fmul-v67.ll | 14 ; CHECK-DAG: [[R11:(r[0-9]+:[0-9]+)]] = dfmpyfix(r3:2,r1:0)
15 ; CHECK: [[R12:(r[0-9]+:[0-9]+)]] = dfmpyll([[R10]],[[R11]])
16 ; CHECK: [[R12]] += dfmpylh([[R10]],[[R11]])
17 ; CHECK: [[R12]] += dfmpylh([[R11]],[[R10]])
18 ; CHECK: [[R12]] += dfmpyhh([[R10]],[[R11]])
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | inline-asm-clobber.ll | 10 ; CHECK: warning: inline asm clobber list contains reserved registers: R11
12 ; RWPI: warning: inline asm clobber list contains reserved registers: R11
13 ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC
14 ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
|
| /external/llvm-project/compiler-rt/lib/builtins/hexagon/ |
| D | fastmath_dlib_asm.S | 77 #define minmin R11:10 // exactly 0x800000000000000000LL
78 #define minminh R11
212 #define minmin R11:10 // exactly 0x800000000000000000LL
213 #define minminh R11
331 #define lmantc R11:10
332 #define mantch R11
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
|
| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 37 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
51 R11)>;
57 R11, CP, DP, SP, LR)> {
|