/external/rust/crates/quiche/deps/boringssl/src/crypto/poly1305/ |
D | poly1305_vec.c | 77 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member 122 p->R20.d[1] = (uint32_t)(r0); in CRYPTO_poly1305_init() 123 p->R20.d[3] = (uint32_t)(r0 >> 32); in CRYPTO_poly1305_init() 163 r0 = ((uint64_t)p->R20.d[3] << 32) | (uint64_t)p->R20.d[1]; in poly1305_first_block() 193 p->R20.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)(r20)&0x3ffffff), in poly1305_first_block() 215 p->R20.d[1] = (uint32_t)(r0); in poly1305_first_block() 216 p->R20.d[3] = (uint32_t)(r0 >> 32); in poly1305_first_block() 260 T0 = _mm_mul_epu32(H0, p->R20.v); in poly1305_blocks() 266 T6 = _mm_mul_epu32(H1, p->R20.v); in poly1305_blocks() 285 T5 = _mm_mul_epu32(H2, p->R20.v); in poly1305_blocks() [all …]
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/external/boringssl/src/crypto/poly1305/ |
D | poly1305_vec.c | 77 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member 126 p->R20.d[1] = (uint32_t)(r0); in CRYPTO_poly1305_init() 127 p->R20.d[3] = (uint32_t)(r0 >> 32); in CRYPTO_poly1305_init() 167 r0 = ((uint64_t)p->R20.d[3] << 32) | (uint64_t)p->R20.d[1]; in poly1305_first_block() 197 p->R20.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)(r20)&0x3ffffff), in poly1305_first_block() 219 p->R20.d[1] = (uint32_t)(r0); in poly1305_first_block() 220 p->R20.d[3] = (uint32_t)(r0 >> 32); in poly1305_first_block() 264 T0 = _mm_mul_epu32(H0, p->R20.v); in poly1305_blocks() 270 T6 = _mm_mul_epu32(H1, p->R20.v); in poly1305_blocks() 289 T5 = _mm_mul_epu32(H2, p->R20.v); in poly1305_blocks() [all …]
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/external/rust/crates/ring/crypto/poly1305/ |
D | poly1305_vec.c | 81 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member 130 p->R20.d[1] = (uint32_t)(r0); in GFp_poly1305_init() 131 p->R20.d[3] = (uint32_t)(r0 >> 32); in GFp_poly1305_init() 171 r0 = ((uint64_t)p->R20.d[3] << 32) | (uint64_t)p->R20.d[1]; in poly1305_first_block() 201 p->R20.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)(r20)&0x3ffffff), in poly1305_first_block() 223 p->R20.d[1] = (uint32_t)(r0); in poly1305_first_block() 224 p->R20.d[3] = (uint32_t)(r0 >> 32); in poly1305_first_block() 268 T0 = _mm_mul_epu32(H0, p->R20.v); in poly1305_blocks() 274 T6 = _mm_mul_epu32(H1, p->R20.v); in poly1305_blocks() 293 T5 = _mm_mul_epu32(H2, p->R20.v); in poly1305_blocks() [all …]
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/external/llvm-project/llvm/test/CodeGen/Hexagon/ |
D | fmul-v67.ll | 26 ; CHECK-DAG: [[R20:(r[0-9]+:[0-9]+)]] = dfmpyfix(r1:0,r3:2) 28 ; CHECK: [[R22:(r[0-9]+:[0-9]+)]] = dfmpyll([[R20]],[[R21]]) 29 ; CHECK: [[R22]] += dfmpylh([[R20]],[[R21]]) 30 ; CHECK: [[R22]] += dfmpylh([[R21]],[[R20]]) 31 ; CHECK: [[R22]] += dfmpyhh([[R20]],[[R21]])
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D | rotate-multi.ll | 38 ; CHECK: r[[R20:[0-9]+]] = asl(r0,#11) 41 ; CHECK: r[[R20]] |= asl(r1,#19) 42 ; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])
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D | bit-cmp0.mir | 50 # CHECK: %[[R20:[0-9]+]]:intregs = A2_tfrsi 0 51 # CHECK: $r0 = COPY %[[R20]]
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D | rdf-copy-undef.ll | 4 ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with
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/external/llvm-project/llvm/test/CodeGen/AVR/ |
D | zext.ll | 12 ; zext R25:R24, R20 13 ; mov R24, R20
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/external/llvm-project/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 64 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 95 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 111 def R20R19 : AVRReg<19, "r20:r19", [R19, R20]>, DwarfRegNum<[19]>; 127 add R24, R25, R18, R19, R20, R21, R22, R23, 145 add R24, R25, R18, R19, R20, R21, R22, R23, 155 add R23, R22, R21, R20, R19, R18, R17, R16
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/external/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 65 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 119 add R24, R25, R18, R19, R20, R21, R22, R23, 137 add R24, R25, R18, R19, R20, R21, R22, R23, 147 add R23, R22, R21, R20, R19, R18, R17, R16
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D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 64 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 95 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 116 add R24, R25, R18, R19, R20, R21, R22, R23, 134 add R24, R25, R18, R19, R20, R21, R22, R23, 144 add R23, R22, R21, R20, R19, R18, R17, R16
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D | AVRCallingConv.td | 20 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
D | ARCRegisterInfo.td | 52 def R20 : Core<20, "%r20">, DwarfRegNum<[20]>; 73 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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/external/llvm-project/llvm/lib/Target/ARC/ |
D | ARCRegisterInfo.td | 52 def R20 : Core<20, "%r20">, DwarfRegNum<[20]>; 73 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/ |
D | ppc_asm.h | 21 #define R20 r20 macro
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/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
D | ppc_asm.h | 16 #define R20 r20 macro
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 89 case Lanai::R20: in getLanaiRegisterNumbering()
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/external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 89 case Lanai::R20: in getLanaiRegisterNumbering()
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 90 case Lanai::R20: in getLanaiRegisterNumbering()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs() 117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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/external/llvm/test/CodeGen/Mips/ |
D | atomic.ll | 253 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24 254 ; NO-SEB-SEH: sra $2, $[[R20]], 24 390 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24 391 ; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24 396 ; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]]
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs() 119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs() 119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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/external/llvm-project/llvm/test/MC/Hexagon/ |
D | two-extenders.s | 129 memh(##0x1000) = R20
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