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Searched refs:R32 (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/test/TableGen/
DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/external/llvm-project/llvm/test/TableGen/
DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/external/python/cpython2/Modules/
Dshamodule.c130 #define R32(x,n) ((x << n) | (x >> (32 - n))) macro
135 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; \
136 E = D; D = C; C = R32(B,30); B = A; A = T
141 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; B = R32(B,30)
144 E = R32(T,5) + f##n(A,B,C) + D + *WP++ + CONST##n; A = R32(A,30)
147 D = R32(E,5) + f##n(T,A,B) + C + *WP++ + CONST##n; T = R32(T,30)
150 C = R32(D,5) + f##n(E,T,A) + B + *WP++ + CONST##n; E = R32(E,30)
153 B = R32(C,5) + f##n(D,E,T) + A + *WP++ + CONST##n; D = R32(D,30)
156 A = R32(B,5) + f##n(C,D,E) + T + *WP++ + CONST##n; C = R32(C,30)
173 W[i] = R32(W[i], 1); in sha_transform()
/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/
Darm-legalize-divmod.mir136 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
145 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
188 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
197 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
242 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
251 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
294 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
303 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
430 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
437 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
[all …]
Darm-legalize-bitcounts.mir120 ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
123 ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
166 ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
169 ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
/external/deqp-deps/amber/tests/cases/
Dssbo_with_graphics_pipeline.vkscript46 # R32 G32 R32 G32 B32 B32
Dmultiple_ubo_update_with_graphics_pipeline.vkscript70 # R32 G32 R32 G32 B32 B32
Dmultiple_ssbo_update_with_graphics_pipeline.vkscript76 # R32 G32 R32 G32 B32 B32
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_formats.c176 F3(A, L32_FLOAT, R32_FLOAT, R, R, R, xx, FLOAT, R32, TB),
177 I3(A, L32_SINT, R32_SINT, R, R, R, xx, SINT, R32, TR),
178 I3(A, L32_UINT, R32_UINT, R, R, R, xx, UINT, R32, TR),
189 C4(A, I32_FLOAT, R32_FLOAT, R, R, R, R, FLOAT, R32, TR),
190 C4(A, I32_SINT, R32_SINT, R, R, R, R, SINT, R32, TR),
191 C4(A, I32_UINT, R32_UINT, R, R, R, R, UINT, R32, TR),
202 A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, R, FLOAT, R32, T),
203 A1(A, A32_SINT, R32_SINT, xx, xx, xx, R, SINT, R32, T),
204 A1(A, A32_UINT, R32_UINT, xx, xx, xx, R, UINT, R32, T),
307 F1(A, R32_FLOAT, R32_FLOAT, R, xx, xx, xx, FLOAT, R32, IB),
[all …]
/external/mesa3d/src/gallium/drivers/zink/
Dzink_format.c34 MAP_FORMAT_INT(R32)
35 MAP_FORMAT_FLOAT(R32)
/external/angle/src/image_util/
Dimageformats.h294 struct R32 struct
298 static void readColor(gl::ColorF *dst, const R32 *src); argument
299 static void readColor(gl::ColorUI *dst, const R32 *src);
300 static void writeColor(R32 *dst, const gl::ColorF *src);
301 static void writeColor(R32 *dst, const gl::ColorUI *src);
302 static void average(R32 *dst, const R32 *src1, const R32 *src2);
Dimageformats.cpp726 void R32::readColor(gl::ColorUI *dst, const R32 *src) in readColor()
734 void R32::readColor(gl::ColorF *dst, const R32 *src) in readColor()
742 void R32::writeColor(R32 *dst, const gl::ColorUI *src) in writeColor()
747 void R32::writeColor(R32 *dst, const gl::ColorF *src) in writeColor()
752 void R32::average(R32 *dst, const R32 *src1, const R32 *src2) in average()
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Df16-instructions.ll37 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
38 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
53 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
54 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
70 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;
71 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
86 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;
87 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
102 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
103 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
[all …]
/external/llvm/test/CodeGen/X86/
D2006-05-08-CoalesceSubRegClass.ll1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/external/llvm-project/llvm/test/CodeGen/X86/
D2006-05-08-CoalesceSubRegClass.ll2 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/external/angle/src/libANGLE/renderer/
DFormat_table_autogen.cpp211 …ID::R32_UINT, GL_R32UI, GL_R32UI, GenerateMip<R32>, NoCopyFunctions, ReadColor<R32, GLuint>, Write…
212 …ORM_ANGLEX, GL_R32_UNORM_ANGLEX, GenerateMip<R32>, NoCopyFunctions, ReadColor<R32, GLfloat>, Write…
213 …ED_ANGLEX, GL_R32_USCALED_ANGLEX, GenerateMip<R32>, NoCopyFunctions, ReadColor<R32, GLuint>, Write…
/external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-intrinsics-gfx8.ll47 ; CHECK-NEXT: [[R32:%.*]] = fpext half [[R:%.*]] to float
48 …cn.image.sample.3d.v4f32.f32(i32 15, float [[S32]], float [[T32]], float [[R32]], <8 x i32> [[RSRC…
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dfunnel-shift.ll32 ; CHECK: r[[R32:[0-9]+]] = sub(#64,r4)
33 ; CHECK: r[[R30]]:[[R31]] |= lsr(r3:2,r[[R32]])
Drotate.ll42 ; CHECK: r[[R32:[0-9]+]]:[[R33:[0-9]+]] = lsr(r[[R30]]:[[R31]],r1)
/external/mesa3d/src/gallium/frontends/lavapipe/
Dlvp_formats.c93 FLOAT_NAME(R32),
/external/autotest/docs/
Dtest-that.md98 test_that -b peach_pit :lab: suite:pyauto_perf -i 'peach_pit-release/R32-4763.0.0'

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