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Searched refs:R4 (Results 1 – 25 of 493) sorted by relevance

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/external/libxaac/decoder/armv7/
Dixheaacd_rescale_subbandsamples.s26 STMFD SP!, {R4-R11, R14}
27 LDR R4, [SP, #44]
30 MOVS R4, R4
40 CMP R4, #31
41 MOVGT R4, #31
42 CMP R4, #-31
43 MOVLT R4, #-31
51 MOVS R4, R4
63 MOV R11, R11, LSL R4
66 MOVGE R5, R5, LSL R4
[all …]
Dixheaacd_calcmaxspectralline.s28 STMFD sp!, {R4-R12, R14}
29 MOV R4, R1, LSR #3
30 MOV R6, R4, LSL #3
42 SUBS R4, R4, #1
51 VMOV.32 R4, D6[0]
54 ORR R4, R4, R1
56 ORR R4, R4, R2
59 ORR R4, R4, R3
66 ORR R4, R4, R2
72 MOVS R0, R4
[all …]
Dixheaacd_enery_calc_per_subband.s30 MOV R4, R2
41 SUBS R5, R5, R4
55 ADD R0, R0, R4, LSL #2
64 ADD R0, R0, R4, LSL #2
82 LDR R4, [R8], #0x100
84 EOR R4, R4, R4, ASR #31
85 ORR R6, R6, R4
101 LDR R4, [R8], #0x100
104 MOV R4, R4, ASR R14
105 SMLABB R6, R4, R4, R6
[all …]
Dixheaacd_tns_parcor2lpc_32x16.s26 STMFD SP!, {R2, R4-R12, R14}
28 MOV R4, SP
36 STR R6, [R4], #4
37 STR R6, [R4, #60]
41 SUB R4, R4, #64
49 LDRSH R2, [R4], #2
61 STRH R14, [R4, #62]
68 @ LDRGTSH R2, [R4], #2
70 LDRSHGT R2, [R4], #2
74 LDRSH R2, [R4, #62]
[all …]
Dixheaacd_esbr_fwd_modulation.s32 LDR R4, [R3]
33 ADD R5, R0, R4, LSL #3
58 SUBS R4, R4, #8
64 LDR R4, [SP, #124]
68 ADD R2, R4, R5
69 ADD R3, R4, #0xB8
76 LDRSH R4, [R3, #0x2C]
79 SUB R4, R4, R5
97 SUBS R4, R4, #2
Dixheaacd_apply_rot.s27 STMFD SP!, {R4-R12, R14}
29 MOV R4, #22
60 SUBS R4, R4, #2
73 MOVW R4, #0x53C
75 ADD R11, R0, R4
76 MOV R4, #10
115 SUBS R4, R4, #1
127 MOV R4, #12
146 SUBS R4, R4, #1
149 MOV R4, #3
[all …]
Dixheaacd_overlap_add1.s29 STMFD sp!, {R4-R12, R14}
32 LDR R4, [SP, #104]
46 VDUP.16 Q11, R4
61 MOV R4, R6, LSL #1
62 RSB R4, R4, #0
124 VST1.16 D26[0], [R11], R4
126 VST1.16 D26[1], [R11], R4
128 VST1.16 D26[2], [R11], R4
130 VST1.16 D26[3], [R11], R4
176 VST1.16 D26[0], [R11], R4
[all …]
Dixheaacd_overlap_add2.s28 STMFD sp!, {R4-R12, R14}
31 LDR R4, [SP, #104]
34 RSB R4, R4, #15
35 CMP R4, #31
36 MOVGT R4, #31
37 SUB R9, R4, #1
40 RSB R4, R4, #0
41 VDUP.32 Q11, R4
52 ADD R4, R4, #1
55 MOV R4, #0x8000
[all …]
Dixheaacd_dec_DCT2_64_asm.s39 MOV R4, #-4
93 ADD R4, R2, #30
95 SUB R4, R4, #6
98 VLD1.16 D10, [R4], R10
134 VLD1.16 D10, [R4], R10
178 VLD1.16 D10, [R4], R10
231 VLD1.16 D10, [R4], R10
309 SUB R4, R1, #2
329 SUB R4, R4, #6
383 VST1.16 D24, [R4]
[all …]
/external/llvm-project/flang/unittests/Evaluate/
Dfolding.cpp41 using R4 = Type<TypeCategory::Real, 4>; in TestHostRuntimeSubnormalFlushing() typedef
42 if constexpr (std::is_same_v<host::HostType<R4>, float>) { in TestHostRuntimeSubnormalFlushing()
52 DynamicType r4{R4{}.GetType()}; in TestHostRuntimeSubnormalFlushing()
56 const Scalar<R4> x1{Scalar<R4>::Word{0x00400000}}; in TestHostRuntimeSubnormalFlushing()
57 Scalar<R4> y1Flushing{CallHostRt<R4>(*callable, flushingContext, x1)}; in TestHostRuntimeSubnormalFlushing()
58 Scalar<R4> y1NoFlushing{CallHostRt<R4>(*callable, noFlushingContext, x1)}; in TestHostRuntimeSubnormalFlushing()
64 std::abs(host::CastFortranToHost<R4>(y1Flushing) + 88.) > 2); in TestHostRuntimeSubnormalFlushing()
66 std::abs(host::CastFortranToHost<R4>(y1NoFlushing) + 88.) < 2); in TestHostRuntimeSubnormalFlushing()
/external/mesa3d/src/util/sha1/
Dsha1.c44 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
86 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
87 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
88 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
89 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
90 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/external/selinux/libselinux/src/
Dsha1.c57 #define R4(v,w,x,y,z,i) z += (w^x^y) + blk(i) + 0xCA62C1D6 + rol(v,5); w=rol(w,30); macro
106 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in TransformFunction()
107 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in TransformFunction()
108 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in TransformFunction()
109 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in TransformFunction()
110 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in TransformFunction()
/external/ppp/pppd/
Dsha1.c40 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
84 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1_Transform()
85 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1_Transform()
86 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1_Transform()
87 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1_Transform()
88 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1_Transform()
/external/wpa_supplicant_8/src/crypto/
Dsha1-internal.c155 #define R4(v,w,x,y,z,i) \ macro
213 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
214 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
215 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
216 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
217 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/external/openssh/openbsd-compat/
Dsha1.c46 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); macro
88 R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); in SHA1Transform()
89 R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); in SHA1Transform()
90 R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); in SHA1Transform()
91 R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); in SHA1Transform()
92 R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); in SHA1Transform()
/external/llvm/test/CodeGen/ARM/Windows/
Dvla.ll16 ; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #7
17 ; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #7
18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
22 ; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #7
23 ; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #7
24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
/external/llvm-project/llvm/test/CodeGen/ARM/Windows/
Dvla.ll16 ; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #7
17 ; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #4
18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
22 ; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #7
23 ; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #4
24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
/external/llvm/test/CodeGen/Thumb/
Dldm-stm-base-materialization-thumb2.ll17 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
18 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
39 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
58 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
60 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
79 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/external/llvm/test/CodeGen/ARM/
Dldm-stm-base-materialization.ll17 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R…
18 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
39 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
58 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
60 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
79 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb/
Dldm-stm-base-materialization-thumb2.ll17 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
18 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
39 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
58 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
60 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
79 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dldm-stm-base-materialization.ll17 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R…
18 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
39 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
58 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
60 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
79 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/external/llvm/test/CodeGen/Mips/
Dcttz-v.ll12 ; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32
13 ; MIPS32-DAG: subu $2, $[[R4]], $[[R3]]
19 ; MIPS32-DAG: subu $3, $[[R4]], $[[R8]]
26 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
27 ; MIPS64-DAG: subu $2, $[[R4]], $[[R3]]
34 ; MIPS64-DAG: subu $3, $[[R4]], $[[R8]]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
27 ; MIPS32-DAG: st.b [[R4]], 0([[R2]])
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
48 ; MIPS32-DAG: st.h [[R4]], 0([[R2]])
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
69 ; MIPS32-DAG: st.w [[R4]], 0([[R2]])
89 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
90 ; MIPS32-DAG: st.d [[R4]], 0([[R2]])
104 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
105 ; MIPS32-DAG: st.d [[R4]], 0([[R2]])
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
Dcomc597.mme.h152 ADD, R4, LOAD1, ZERO, 0, NONE, NONE),
157 MME_INSN(0, ADD, ZERO, R4, ZERO, 0, NONE, ALU0,
203 MME_INSN(0, STATE, R4, IMMED, ZERO, 0x2100/4, NONE, NONE,
215 MME_INSN(0, OR, R7, R3, R4, 0, NONE, NONE,
247 MME_INSN(0, STATE, R4, IMMED, ZERO, 0x2100/4, NONE, NONE,
259 MME_INSN(0, OR, R7, R3, R4, 0, NONE, NONE,
291 MME_INSN(0, STATE, R4, IMMED, ZERO, 0x20c0/4, NONE, NONE,
303 MME_INSN(0, OR, R7, R1, R4, 0, NONE, NONE,
335 MME_INSN(0, STATE, R4, IMMED, ZERO, 0x2100/4, NONE, NONE,
347 MME_INSN(0, OR, R7, R1, R4, 0, NONE, NONE,
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dcttz-v.ll12 ; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32
13 ; MIPS32-DAG: subu $2, $[[R4]], $[[R3]]
19 ; MIPS32-DAG: subu $3, $[[R4]], $[[R8]]
26 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
27 ; MIPS64-DAG: subu $[[R5:[0-9]+]], $[[R4]], $[[R3]]
35 ; MIPS64-DAG: subu $[[R13:[0-9]+]], $[[R4]], $[[R12]]

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