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Searched refs:R600 (Results 1 – 25 of 224) sorted by relevance

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/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.cpp28 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
29 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel()
30 R600::sub8, R600::sub9, R600::sub10, R600::sub11, in getSubRegFromChannel()
31 R600::sub12, R600::sub13, R600::sub14, R600::sub15 in getSubRegFromChannel()
44 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
47 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
48 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
49 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
[all …]
DR600InstrInfo.cpp66 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
67 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
68 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
69 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
71 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
72 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
73 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
74 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
81 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
88 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
[all …]
DR600ControlFlowFinalizer.cpp96 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
105 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
106 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
107 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
108 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
169 case R600::CF_PUSH_EG: in pushBranch()
170 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
241 case R600::KILL: in IsTrivialInst()
242 case R600::RETURN: in IsTrivialInst()
254 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
[all …]
DR600ExpandSpecialInstrs.cpp98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
105 R600::OpName::pred_sel); in runOnMachineFunction()
107 R600::OpName::pred_sel); in runOnMachineFunction()
116 case R600::PRED_X: { in runOnMachineFunction()
124 R600::ZERO); // src1 in runOnMachineFunction()
127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
134 case R600::DOT_4: { in runOnMachineFunction()
[all …]
DR600EmitClauseMarkers.cpp54 case R600::INTERP_PAIR_XY: in OccupiedDwords()
55 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
56 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
57 case R600::DOT_4: in OccupiedDwords()
59 case R600::KILL: in OccupiedDwords()
79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
91 case R600::PRED_X: in isALU()
92 case R600::INTERP_PAIR_XY: in isALU()
93 case R600::INTERP_PAIR_ZW: in isALU()
94 case R600::INTERP_VEC_LOAD: in isALU()
[all …]
DR600ClauseMergePass.cpp36 case R600::CF_ALU: in isCFAlu()
37 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
127 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
[all …]
DR600MachineScheduler.cpp164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
183 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
226 case R600::PRED_X: in getAluKind()
228 case R600::INTERP_PAIR_XY: in getAluKind()
229 case R600::INTERP_PAIR_ZW: in getAluKind()
230 case R600::INTERP_VEC_LOAD: in getAluKind()
231 case R600::DOT_4: in getAluKind()
233 case R600::COPY: in getAluKind()
249 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
260 case R600::sub0: in getAluKind()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp66 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
67 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
68 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
69 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
71 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
72 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
73 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
74 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
81 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
88 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
[all …]
DR600RegisterInfo.cpp37 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
38 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
39 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
40 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
41 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
42 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ALU_CONST); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); in getReservedRegs()
[all …]
DR600ControlFlowFinalizer.cpp96 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
105 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
106 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
107 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
108 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
170 case R600::CF_PUSH_EG: in pushBranch()
171 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
242 case R600::KILL: in IsTrivialInst()
243 case R600::RETURN: in IsTrivialInst()
255 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
[all …]
DR600ExpandSpecialInstrs.cpp98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
105 R600::OpName::pred_sel); in runOnMachineFunction()
107 R600::OpName::pred_sel); in runOnMachineFunction()
116 case R600::PRED_X: { in runOnMachineFunction()
124 R600::ZERO); // src1 in runOnMachineFunction()
127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
134 case R600::DOT_4: { in runOnMachineFunction()
[all …]
DR600EmitClauseMarkers.cpp54 case R600::INTERP_PAIR_XY: in OccupiedDwords()
55 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
56 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
57 case R600::DOT_4: in OccupiedDwords()
59 case R600::KILL: in OccupiedDwords()
79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
91 case R600::PRED_X: in isALU()
92 case R600::INTERP_PAIR_XY: in isALU()
93 case R600::INTERP_PAIR_ZW: in isALU()
94 case R600::INTERP_VEC_LOAD: in isALU()
[all …]
DR600ClauseMergePass.cpp36 case R600::CF_ALU: in isCFAlu()
37 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
127 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
[all …]
DR600MachineScheduler.cpp164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
183 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
226 case R600::PRED_X: in getAluKind()
228 case R600::INTERP_PAIR_XY: in getAluKind()
229 case R600::INTERP_PAIR_ZW: in getAluKind()
230 case R600::INTERP_VEC_LOAD: in getAluKind()
231 case R600::DOT_4: in getAluKind()
233 case R600::COPY: in getAluKind()
249 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
260 case R600::sub0: in getAluKind()
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dudivrem.ll2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s
7 ; R600-LABEL: test_udivrem:
8 ; R600: ; %bb.0:
9 ; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[]
10 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
11 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
12 ; R600-NEXT: CF_END
13 ; R600-NEXT: ALU clause starting at 4:
14 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[9].X,
15 ; R600-NEXT: RECIP_UINT * T0.X, KC0[9].X,
[all …]
Dfshl.ll5 …: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,R600
62 ; R600-LABEL: fshl_i32:
63 ; R600: ; %bb.0: ; %entry
64 ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
65 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
66 ; R600-NEXT: CF_END
67 ; R600-NEXT: PAD
68 ; R600-NEXT: ALU clause starting at 4:
69 ; R600-NEXT: LSHR T0.Z, KC0[2].Z, 1,
70 ; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, 1,
[all …]
Dnullptr.ll2 …lc < %s -march=r600 -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s
12 ; R600-NEXT: .long 0
17 ; R600-NEXT: .long 0
29 ; R600-NEXT: .long 0
33 ; R600-NEXT: .long 0
37 ; R600-NEXT: .long 0
41 ; R600-NEXT: .long 0
45 ; R600-NEXT: .long 0
49 ; R600-NEXT: .long 0
53 ; R600-NEXT: .long 0
[all …]
Dfadd.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
[all …]
Dbuild_vector.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MOV
23 ; R600: MOV
[all …]
Dfdiv.ll5 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
14 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
15 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
41 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
42 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
116 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
117 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
131 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
132 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
146 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfdiv.ll6 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
15 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
16 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
38 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
39 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
54 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
55 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
70 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
71 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
72 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
[all …]
Dfadd.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
[all …]
Dsetcc.ll2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
18 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ; R600: SETE_DX10
49 ; R600: SETGT_DX10
60 ; R600: SETGE_DX10
[all …]
Dbuild_vector.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MOV
23 ; R600: MOV
[all …]
Duint_to_fp.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
33 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]

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