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Searched refs:RADV_CMD_FLAG_WB_L2 (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c1078 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) { in gfx10_cs_emit_cache_flush()
1372 RADV_CMD_FLAG_WB_L2 | in si_cs_emit_cache_flush()
1408 RADV_CMD_FLAG_WB_L2))) && in si_cs_emit_cache_flush()
1417 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) { in si_cs_emit_cache_flush()
1427 if(flush_bits & RADV_CMD_FLAG_WB_L2) { in si_cs_emit_cache_flush()
Dradv_meta_buffer.c400 RADV_CMD_FLAG_WB_L2; in radv_fill_buffer()
Dradv_private.h1062 RADV_CMD_FLAG_WB_L2 = 1 << 4, enumerator
Dradv_cmd_buffer.c3206 flush_bits |= RADV_CMD_FLAG_WB_L2; in radv_src_access_flush()
3230 RADV_CMD_FLAG_WB_L2 | in radv_src_access_flush()
4149 …lush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2; in radv_EndCommandBuffer()
Dradv_meta_clear.c974 RADV_CMD_FLAG_WB_L2; in clear_htile_mask()