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Searched refs:RBGPR (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo() local
145 (void)RBGPR; in ARMRegisterBankInfo()
146 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo() local
143 (void)RBGPR; in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local
36 (void)RBGPR; in AArch64RegisterBankInfo()
37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
39 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in AArch64RegisterBankInfo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo() local
33 (void)RBGPR; in X86RegisterBankInfo()
34 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization."); in X86RegisterBankInfo()
38 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()
40 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in X86RegisterBankInfo()
/external/llvm-project/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo() local
33 (void)RBGPR; in X86RegisterBankInfo()
34 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization."); in X86RegisterBankInfo()
38 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()
40 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in X86RegisterBankInfo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local
52 (void)RBGPR; in AArch64RegisterBankInfo()
53 assert(&AArch64::GPRRegBank == &RBGPR && in AArch64RegisterBankInfo()
67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
69 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in AArch64RegisterBankInfo()
102 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); in AArch64RegisterBankInfo()
103 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); in AArch64RegisterBankInfo()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64RegisterBankInfo.cpp51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local
52 (void)RBGPR; in AArch64RegisterBankInfo()
53 assert(&AArch64::GPRRegBank == &RBGPR && in AArch64RegisterBankInfo()
68 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
70 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in AArch64RegisterBankInfo()
103 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); in AArch64RegisterBankInfo()
104 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); in AArch64RegisterBankInfo()