| /external/llvm-project/llvm/test/MC/X86/ |
| D | intel-syntax-error.s | 30 lea RDX, [unknown_number * RAX + RBX + _foo]
32 lea RDX, [4 * RAX + 27 * RBX + _pat]
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| D | intel-syntax.s | 17 lea RDX, [8 * RAX + RBX + _foo]
19 lea RDX, [_foo + 8 * RAX + RBX]
27 lea RDX, [_foo + RAX * 8 + RBX]
39 lea RDX, [RAX * number + RBX + _foo]
41 lea RDX, [_foo + RAX * number + RBX]
47 lea RDX, [number * RAX + RBX + _foo]
49 lea RDX, [_foo + number * RAX + RBX]
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| /external/swiftshader/third_party/marl/src/ |
| D | osfiber_asm_x64.h | 38 uintptr_t RBX; member
56 static_assert(offsetof(marl_fiber_context, RBX) == MARL_REG_RBX,
|
| /external/llvm-project/llvm/test/tools/llvm-objdump/COFF/ |
| D | win64-unwind-data.test | 16 OBJ-NEXT: Frame register: RBX
20 OBJ-NEXT: 0x0f: UOP_PushNonVol RBX
65 EXE-NEXT: Frame register: RBX
69 EXE-NEXT: 0x0f: UOP_PushNonVol RBX
|
| /external/llvm/test/tools/llvm-objdump/ |
| D | win64-unwind-data.test | 16 OBJ-NEXT: Frame register: RBX
20 OBJ-NEXT: 0x0f: UOP_PushNonVol RBX
65 EXE-NEXT: Frame register: RBX
69 EXE-NEXT: 0x0f: UOP_PushNonVol RBX
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
421 return X86::RBX; in getX86SubSuperRegisterOrZero()
|
| /external/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/ |
| D | debug_loclists.s | 19 # BOTH-NEXT: <default>: DW_OP_reg3 RBX
41 # REGULAR-NEXT: <default>: DW_OP_reg3 RBX
43 # VERBOSE-NEXT: => <default>: DW_OP_reg3 RBX
|
| /external/strace/linux/x86_64/ |
| D | arch_regs.h | 10 #define RBX 5 macro
|
| D | userent.h | 6 XLAT(8*RBX),
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 38 #define RBX 40 macro
|
| /external/llvm-project/llvm/test/DebugInfo/MIR/X86/ |
| D | debug-call-site-param.mir | 31 # CHECK-GNU-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg3 RBX+0)
37 # CHECK-GNU-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg15 R15+0, DW_OP_breg3 RBX+0, DW_OP_pl…
57 # CHECK-DWARF5-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0)
63 # CHECK-DWARF5-NEXT: DW_AT_call_value (DW_OP_breg15 R15+0, DW_OP_breg3 RBX+0, DW_OP_plus)
|
| D | dbgcall-site-two-fwd-reg-defs.mir | 137 # CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_con…
141 # CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0)
|
| /external/llvm-project/llvm/test/tools/llvm-exegesis/X86/ |
| D | analysis-clustering-algorithms.test | 193 - 'ROL64ri RBX RBX i_0x1'
210 - 'RBX=0x0'
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 157 {codeview::RegisterId::RBX, X86::RBX}, in initLLVMToSEHAndCVRegMapping()
621 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
670 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
706 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
742 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
743 return X86::RBX; in getX86SubSuperRegisterOrZero()
|
| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 155 {codeview::RegisterId::RBX, X86::RBX}, in initLLVMToSEHAndCVRegMapping()
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
645 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
682 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
718 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
754 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
755 return X86::RBX; in getX86SubSuperRegisterOrZero()
|
| /external/llvm-project/lld/test/COFF/ |
| D | unwind.test | 29 # UNWIND: Frame register: RBX
33 # UNWIND: 0x0f: UOP_PushNonVol RBX
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ExpandPseudo.cpp | 351 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false); in ExpandMI()
358 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, in ExpandMI()
456 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true); in ExpandMI()
|
| D | X86CallingConv.td | 427 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
590 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
684 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
1077 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1084 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1113 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1128 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1139 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1143 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1155 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15,
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
584 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
678 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
1070 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1077 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1106 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1121 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1132 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1136 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1148 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
373 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
463 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
856 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
863 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
888 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
912 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
916 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
928 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
|
| /external/rust/crates/libc/src/fuchsia/ |
| D | x86_64.rs | 126 pub const RBX: ::c_int = 5; constant
|
| /external/lzma/Asm/x86/ |
| D | 7zAsm.asm | 82 r3 equ RBX
|
| /external/llvm-project/llvm/test/DebugInfo/X86/ |
| D | location-range-inlined-xblock.mir | 27 ## Check that the location for inlined variable 'local' (RBX), which spans
30 # CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_reg3 RBX)
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 71 RBX = 51,
1966 …, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15…
1996 …, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15…
2006 …, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15…
2026 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2086 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2116 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2206 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2266 X86::RSI, X86::RBX,
2276 X86::RCX, X86::RBX,
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 176 ENTRY(RBX) \
194 ENTRY(RBX) \
|