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Searched refs:RC2 (Results 1 – 25 of 40) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatternsV65.td40 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
43 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
49 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
52 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
58 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
61 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
DHexagonGenInsert.cpp341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
342 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
344 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
359 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2); in operator ()() local
360 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
374 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPatternsV65.td40 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
43 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
49 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
52 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
58 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
61 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
DHexagonGenInsert.cpp341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
342 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
344 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
359 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2); in operator ()() local
360 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
374 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/jcajce/provider/symmetric/
DRC2.java38 public final class RC2 class
40 private RC2() in RC2() method in RC2
463 private static final String PREFIX = RC2.class.getName();
/external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/jcajce/provider/symmetric/
DRC2.java42 public final class RC2 class
44 private RC2() in RC2() method in RC2
478 private static final String PREFIX = RC2.class.getName();
/external/bouncycastle/repackaged_platform/bcprov/src/main/java/com/android/internal/org/bouncycastle/jcajce/provider/symmetric/
DRC2.java42 public final class RC2 class
44 private RC2() in RC2() method in RC2
478 private static final String PREFIX = RC2.class.getName();
/external/mdnsresponder/mDNSWindows/ControlPanel/res/
DControlPanel.rc22 // CPL_PP.RC2 - resources Microsoft Visual C++ does not edit directly
/external/mdnsresponder/mDNSWindows/DNSServiceBrowser/WindowsCE/Resources/
DApplication.rc22 // APPLICATION.RC2 - resources Microsoft eMbedded Visual C++ does not edit directly
/external/llvm-project/clang/test/Driver/
Dhip-phases.hip105 // RUN: | FileCheck -check-prefixes=RDC2,RC2 %s
119 // RC2-DAG: [[P9:[0-9]+]]: offload, "device-[[T]] (amdgcn-amd-amdhsa:[[ARCH1]])" {[[P6]]}, ir
127 // RC2-DAG: [[P16:[0-9]+]]: offload, "device-[[T]] (amdgcn-amd-amdhsa:[[ARCH2]])" {[[P13]]}, ir
129 // RC2-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
130 // RC2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
131 // RC2-DAG: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (host-[[T]])
132 // RC2-DAG: [[P19:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
133 // RC2-DAG: [[P20:[0-9]+]]: assembler, {[[P19]]}, object, (host-[[T]])
138 // RC2-DAG: [[P23:[0-9]+]]: clang-offload-bundler, {[[P9]], [[P16]], [[P20]]}, object, (host-[[T]])
/external/apache-commons-compress/src/main/java/org/apache/commons/compress/archivers/zip/
DPKWareExtraHeader.java210 RC2(0x6702), enumConstant
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp294 const TargetRegisterClass *RC2 = in expandBuildPairF64() local
299 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2); in expandBuildPairF64()
306 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); in expandBuildPairF64()
358 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64() local
364 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); in expandExtractElementF64()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp318 const TargetRegisterClass *RC2 = in expandBuildPairF64() local
323 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2); in expandBuildPairF64()
330 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64() local
391 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); in expandExtractElementF64()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp318 const TargetRegisterClass *RC2 = in expandBuildPairF64() local
323 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2); in expandBuildPairF64()
330 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64() local
391 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); in expandExtractElementF64()
/external/boringssl/src/crypto/obj/
Dobjects.txt185 pkcs5 4 : PBE-MD2-RC2-64 : pbeWithMD2AndRC2-CBC
186 pkcs5 6 : PBE-MD5-RC2-64 : pbeWithMD5AndRC2-CBC
188 pkcs5 11 : PBE-SHA1-RC2-64 : pbeWithSHA1AndRC2-CBC
347 pkcs12-pbeids 5 : PBE-SHA1-RC2-128 : pbeWithSHA1And128BitRC2-CBC
349 pkcs12-pbeids 6 : PBE-SHA1-RC2-40 : pbeWithSHA1And40BitRC2-CBC
373 rsadsi 3 2 : RC2-CBC : rc2-cbc
374 : RC2-ECB : rc2-ecb
376 : RC2-CFB : rc2-cfb
378 : RC2-OFB : rc2-ofb
379 : RC2-40-CBC : rc2-40-cbc
[all …]
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1874 CodeGenRegisterClass *RC2 = &*I; in inferCommonSubClass() local
1875 if (RC1 == RC2) in inferCommonSubClass()
1880 const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); in inferCommonSubClass()
1892 if (RC2->SpillSize > RC1->SpillSize || in inferCommonSubClass()
1893 (RC2->SpillSize == RC1->SpillSize && in inferCommonSubClass()
1894 RC2->SpillAlignment > RC1->SpillAlignment)) in inferCommonSubClass()
1895 std::swap(RC1, RC2); in inferCommonSubClass()
1898 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
317 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
319 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
335 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2); in operator ()() local
336 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
350 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
/external/grpc-grpc/templates/
Dpackage.xml.template224 <release>1.0.0RC2</release>
225 <api>1.0.0RC2</api>
/external/llvm/docs/
DReleaseProcess.rst40 RC1 and RC2, but not so much at the end of it.
74 * On the pre-release, you should change ``-rc 1`` to ``-final``. On RC2, change it to ``-rc 2`` and…
/external/wayland/
Dreleasing.txt13 $ export RELEASE_NAME="[alpha|beta|RC1|RC2|official|point]"
/external/llvm-project/llvm/docs/
DReleaseProcess.rst42 fixed between RC1 and RC2, but not so much at the end of it.
79 * On the pre-release, you should change ``-rc 1`` to ``-final``. On RC2,
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp2154 CodeGenRegisterClass *RC2 = &*I; in inferCommonSubClass() local
2155 if (RC1 == RC2) in inferCommonSubClass()
2160 const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); in inferCommonSubClass()
2173 if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) in inferCommonSubClass()
2174 std::swap(RC1, RC2); in inferCommonSubClass()
2177 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
/external/hamcrest/
DCHANGES.txt65 == Version 1.3 RC2: Released October 22 2010 ==
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp870 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp() local
892 if (RC2 && isVSSRCRegClass(RC2)) in PPCEmitCmp()
910 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) { in PPCEmitCmp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp() local
890 if (RC2 && isVSSRCRegClass(RC2)) in PPCEmitCmp()
908 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) { in PPCEmitCmp()

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