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Searched refs:RCC_DDRITFCR (Results 1 – 5 of 5) sorted by relevance

/external/arm-trusted-firmware/drivers/st/ddr/
Dstm32mp1_ddr.c742 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
743 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
744 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
745 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
746 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
747 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
756 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
757 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
762 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
804 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
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Dstm32mp1_ddr_helpers.c16 mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, in ddr_enable_clock()
Dstm32mp1_ram.c242 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
247 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
/external/arm-trusted-firmware/drivers/st/clk/
Dstm32mp1_clk.c340 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK),
341 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
342 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK),
343 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
344 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
345 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
346 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
347 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
348 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK),
349 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
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/external/arm-trusted-firmware/include/drivers/st/
Dstm32mp1_rcc.h42 #define RCC_DDRITFCR U(0xD8) macro