1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef _RADEON_VCN_DEC_H 29 #define _RADEON_VCN_DEC_H 30 31 #include "radeon_video.h" 32 33 #define RDECODE_PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) 34 #define RDECODE_PKT_TYPE_G(x) (((x) >> 30) & 0x3) 35 #define RDECODE_PKT_TYPE_C 0x3FFFFFFF 36 #define RDECODE_PKT_COUNT_S(x) (((unsigned)(x)&0x3FFF) << 16) 37 #define RDECODE_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 38 #define RDECODE_PKT_COUNT_C 0xC000FFFF 39 #define RDECODE_PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0) 40 #define RDECODE_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) 41 #define RDECODE_PKT0_BASE_INDEX_C 0xFFFF0000 42 #define RDECODE_PKT0(index, count) \ 43 (RDECODE_PKT_TYPE_S(0) | RDECODE_PKT0_BASE_INDEX_S(index) | RDECODE_PKT_COUNT_S(count)) 44 45 #define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2)) 46 47 #define RDECODE_PKT_REG_J(x) ((unsigned)(x)&0x3FFFF) 48 #define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18) 49 #define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24) 50 #define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28) 51 #define RDECODE_PKTJ(reg, cond, type) \ 52 (RDECODE_PKT_REG_J(reg) | RDECODE_PKT_RES_J(0) | RDECODE_PKT_COND_J(cond) | \ 53 RDECODE_PKT_TYPE_J(type)) 54 55 #define RDECODE_CMD_MSG_BUFFER 0x00000000 56 #define RDECODE_CMD_DPB_BUFFER 0x00000001 57 #define RDECODE_CMD_DECODING_TARGET_BUFFER 0x00000002 58 #define RDECODE_CMD_FEEDBACK_BUFFER 0x00000003 59 #define RDECODE_CMD_PROB_TBL_BUFFER 0x00000004 60 #define RDECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005 61 #define RDECODE_CMD_BITSTREAM_BUFFER 0x00000100 62 #define RDECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204 63 #define RDECODE_CMD_CONTEXT_BUFFER 0x00000206 64 65 #define RDECODE_MSG_CREATE 0x00000000 66 #define RDECODE_MSG_DECODE 0x00000001 67 #define RDECODE_MSG_DESTROY 0x00000002 68 69 #define RDECODE_CODEC_H264 0x00000000 70 #define RDECODE_CODEC_VC1 0x00000001 71 #define RDECODE_CODEC_MPEG2_VLD 0x00000003 72 #define RDECODE_CODEC_MPEG4 0x00000004 73 #define RDECODE_CODEC_H264_PERF 0x00000007 74 #define RDECODE_CODEC_JPEG 0x00000008 75 #define RDECODE_CODEC_H265 0x00000010 76 #define RDECODE_CODEC_VP9 0x00000011 77 78 #define RDECODE_ARRAY_MODE_LINEAR 0x00000000 79 #define RDECODE_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001 80 #define RDECODE_ARRAY_MODE_1D_THIN 0x00000002 81 #define RDECODE_ARRAY_MODE_2D_THIN 0x00000004 82 #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004 83 #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005 84 85 #define RDECODE_H264_PROFILE_BASELINE 0x00000000 86 #define RDECODE_H264_PROFILE_MAIN 0x00000001 87 #define RDECODE_H264_PROFILE_HIGH 0x00000002 88 #define RDECODE_H264_PROFILE_STEREO_HIGH 0x00000003 89 #define RDECODE_H264_PROFILE_MVC 0x00000004 90 91 #define RDECODE_VC1_PROFILE_SIMPLE 0x00000000 92 #define RDECODE_VC1_PROFILE_MAIN 0x00000001 93 #define RDECODE_VC1_PROFILE_ADVANCED 0x00000002 94 95 #define RDECODE_SW_MODE_LINEAR 0x00000000 96 #define RDECODE_256B_S 0x00000001 97 #define RDECODE_256B_D 0x00000002 98 #define RDECODE_4KB_S 0x00000005 99 #define RDECODE_4KB_D 0x00000006 100 #define RDECODE_64KB_S 0x00000009 101 #define RDECODE_64KB_D 0x0000000A 102 #define RDECODE_4KB_S_X 0x00000015 103 #define RDECODE_4KB_D_X 0x00000016 104 #define RDECODE_64KB_S_X 0x00000019 105 #define RDECODE_64KB_D_X 0x0000001A 106 107 #define RDECODE_MESSAGE_NOT_SUPPORTED 0x00000000 108 #define RDECODE_MESSAGE_CREATE 0x00000001 109 #define RDECODE_MESSAGE_DECODE 0x00000002 110 #define RDECODE_MESSAGE_DRM 0x00000003 111 #define RDECODE_MESSAGE_AVC 0x00000006 112 #define RDECODE_MESSAGE_VC1 0x00000007 113 #define RDECODE_MESSAGE_MPEG2_VLD 0x0000000A 114 #define RDECODE_MESSAGE_MPEG4_ASP_VLD 0x0000000B 115 #define RDECODE_MESSAGE_HEVC 0x0000000D 116 #define RDECODE_MESSAGE_VP9 0x0000000E 117 118 #define RDECODE_FEEDBACK_PROFILING 0x00000001 119 120 #define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT 7 121 122 #define NUM_BUFFERS 4 123 124 #define RDECODE_VP9_PROBS_DATA_SIZE 2304 125 126 #define mmUVD_JPEG_CNTL 0x0200 127 #define mmUVD_JPEG_CNTL_BASE_IDX 1 128 #define mmUVD_JPEG_RB_BASE 0x0201 129 #define mmUVD_JPEG_RB_BASE_BASE_IDX 1 130 #define mmUVD_JPEG_RB_WPTR 0x0202 131 #define mmUVD_JPEG_RB_WPTR_BASE_IDX 1 132 #define mmUVD_JPEG_RB_RPTR 0x0203 133 #define mmUVD_JPEG_RB_RPTR_BASE_IDX 1 134 #define mmUVD_JPEG_RB_SIZE 0x0204 135 #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 136 #define mmUVD_JPEG_TIER_CNTL2 0x021a 137 #define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 1 138 #define mmUVD_JPEG_UV_TILING_CTRL 0x021c 139 #define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 1 140 #define mmUVD_JPEG_TILING_CTRL 0x021e 141 #define mmUVD_JPEG_TILING_CTRL_BASE_IDX 1 142 #define mmUVD_JPEG_OUTBUF_RPTR 0x0220 143 #define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 144 #define mmUVD_JPEG_OUTBUF_WPTR 0x0221 145 #define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 146 #define mmUVD_JPEG_PITCH 0x0222 147 #define mmUVD_JPEG_PITCH_BASE_IDX 1 148 #define mmUVD_JPEG_INT_EN 0x0229 149 #define mmUVD_JPEG_INT_EN_BASE_IDX 1 150 #define mmUVD_JPEG_UV_PITCH 0x022b 151 #define mmUVD_JPEG_UV_PITCH_BASE_IDX 1 152 #define mmUVD_JPEG_INDEX 0x023e 153 #define mmUVD_JPEG_INDEX_BASE_IDX 1 154 #define mmUVD_JPEG_DATA 0x023f 155 #define mmUVD_JPEG_DATA_BASE_IDX 1 156 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438 157 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 158 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439 159 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 160 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a 161 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 162 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b 163 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 164 #define mmUVD_CTX_INDEX 0x0528 165 #define mmUVD_CTX_INDEX_BASE_IDX 1 166 #define mmUVD_CTX_DATA 0x0529 167 #define mmUVD_CTX_DATA_BASE_IDX 1 168 #define mmUVD_SOFT_RESET 0x05a0 169 #define mmUVD_SOFT_RESET_BASE_IDX 1 170 171 #define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f 172 #define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e 173 #define vcnipUVD_JRBC_IB_REF_DATA 0x408f 174 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1 175 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0 176 #define vcnipUVD_JPEG_RB_BASE 0x4001 177 #define vcnipUVD_JPEG_RB_SIZE 0x4004 178 #define vcnipUVD_JPEG_RB_WPTR 0x4002 179 #define vcnipUVD_JPEG_PITCH 0x401f 180 #define vcnipUVD_JPEG_UV_PITCH 0x4020 181 #define vcnipJPEG_DEC_ADDR_MODE 0x4027 182 #define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024 183 #define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025 184 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3 185 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2 186 #define vcnipUVD_JPEG_INDEX 0x402c 187 #define vcnipUVD_JPEG_DATA 0x402d 188 #define vcnipUVD_JPEG_TIER_CNTL2 0x400f 189 #define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e 190 #define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c 191 #define vcnipUVD_JPEG_INT_EN 0x400a 192 #define vcnipUVD_JPEG_CNTL 0x4000 193 #define vcnipUVD_JPEG_RB_RPTR 0x4003 194 #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d 195 196 #define UVD_BASE_INST0_SEG0 0x00007800 197 #define UVD_BASE_INST0_SEG1 0x00007E00 198 #define UVD_BASE_INST0_SEG2 0 199 #define UVD_BASE_INST0_SEG3 0 200 #define UVD_BASE_INST0_SEG4 0 201 202 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg) 203 204 #define COND0 0 205 #define COND1 1 206 #define COND2 2 207 #define COND3 3 208 #define COND4 4 209 #define COND5 5 210 #define COND6 6 211 #define COND7 7 212 213 #define TYPE0 0 214 #define TYPE1 1 215 #define TYPE2 2 216 #define TYPE3 3 217 #define TYPE4 4 218 #define TYPE5 5 219 #define TYPE6 6 220 #define TYPE7 7 221 222 /* VP9 Frame header flags */ 223 #define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT (13) 224 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT (12) 225 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT (11) 226 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_SHIFT (10) 227 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT (9) 228 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT (8) 229 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT (7) 230 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT (6) 231 #define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT (5) 232 #define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT (4) 233 #define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT (3) 234 #define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT (2) 235 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT (1) 236 #define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_SHIFT (0) 237 238 #define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK (0x00002000) 239 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK (0x00001000) 240 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK (0x00000800) 241 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_MASK (0x00000400) 242 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK (0x00000200) 243 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK (0x00000100) 244 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK (0x00000080) 245 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK (0x00000040) 246 #define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK (0x00000020) 247 #define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK (0x00000010) 248 #define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK (0x00000008) 249 #define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK (0x00000004) 250 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK (0x00000002) 251 #define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_MASK (0x00000001) 252 253 /* Drm definitions */ 254 #define DRM_CMD_KEY_SHIFT 0 255 #define DRM_CMD_CNT_KEY_SHIFT 1 256 #define DRM_CMD_CNT_DATA_SHIFT 2 257 #define DRM_CMD_OFFSET_SHIFT 3 258 #define DRM_CMD_SESSION_SEL_SHIFT 4 259 #define DRM_CMD_UNWRAP_KEY_SHIFT 8 260 #define DRM_CMD_GEN_MASK_SHIFT 9 261 #define DRM_CMD_ALGORITHM_SHIFT 10 262 #define DRM_CMD_BYTE_MASK_SHIFT 16 263 #define DRM_CMD_DRM_BYPASS_SHIFT 31 264 265 #define DRM_CMD_KEY_MASK (0x00000001) 266 #define DRM_CMD_CNT_KEY_MASK (0x00000002) 267 #define DRM_CMD_CNT_DATA_MASK (0x00000004) 268 #define DRM_CMD_OFFSET_MASK (0x00000008) 269 #define DRM_CMD_SESSION_SEL_MASK (0x000000F0) 270 #define DRM_CMD_UNWRAP_KEY_MASK (0x00000100) 271 #define DRM_CMD_GEN_MASK_MASK (0x00000200) 272 #define DRM_CMD_ALGORITHM_MASK (0x00000C00) 273 #define DRM_CMD_BYTE_MASK_MASK (0x00FF0000) 274 #define DRM_CMD_DRM_BYPASS_MASK (0x80000000) 275 276 /* Drm_cntl definitions */ 277 #define DRM_CNTL_ENC_BYTECNT_SHIFT (6) 278 #define DRM_CNTL_CLR_BYTECNT_SHIFT (16) 279 #define DRM_CNTL_BYPASS_SHIFT (24) 280 #define DRM_CNTL_PARTIAL_MODE_SHIFT (25) 281 #define DRM_CNTL_OFFSET_MODE_SHIFT (26) 282 #define DRM_CNTL_HEADER_MODE_SHIFT (27) 283 #define DRM_CNTL_HEADER_BYTECNT_SHIFT (28) 284 285 #define DRM_CNTL_ENC_BYTECNT_MASK (0x00000FC0) 286 #define DRM_CNTL_CLR_BYTECNT_MASK (0x003F0000) 287 #define DRM_CNTL_BYPASS_MASK (0x01000000) 288 #define DRM_CNTL_PARTIAL_MODE_MASK (0x02000000) 289 #define DRM_CNTL_OFFSET_MODE_MASK (0x04000000) 290 #define DRM_CNTL_HEADER_MODE_MASK (0x08000000) 291 #define DRM_CNTL_HEADER_BYTECNT_MASK (0xF0000000) 292 293 #define SAMU_DRM_DISABLE 0x00000000 294 #define SAMU_DRM_ENABLE 0x00000001 295 296 typedef struct rvcn_dec_message_index_s { 297 unsigned int message_id; 298 unsigned int offset; 299 unsigned int size; 300 unsigned int filled; 301 } rvcn_dec_message_index_t; 302 303 typedef struct rvcn_dec_message_header_s { 304 unsigned int header_size; 305 unsigned int total_size; 306 unsigned int num_buffers; 307 unsigned int msg_type; 308 unsigned int stream_handle; 309 unsigned int status_report_feedback_number; 310 311 rvcn_dec_message_index_t index[1]; 312 } rvcn_dec_message_header_t; 313 314 typedef struct rvcn_dec_message_create_s { 315 unsigned int stream_type; 316 unsigned int session_flags; 317 unsigned int width_in_samples; 318 unsigned int height_in_samples; 319 } rvcn_dec_message_create_t; 320 321 typedef struct rvcn_dec_message_decode_s { 322 unsigned int stream_type; 323 unsigned int decode_flags; 324 unsigned int width_in_samples; 325 unsigned int height_in_samples; 326 327 unsigned int bsd_size; 328 unsigned int dpb_size; 329 unsigned int dt_size; 330 unsigned int sct_size; 331 unsigned int sc_coeff_size; 332 unsigned int hw_ctxt_size; 333 unsigned int sw_ctxt_size; 334 unsigned int pic_param_size; 335 unsigned int mb_cntl_size; 336 unsigned int reserved0[4]; 337 unsigned int decode_buffer_flags; 338 339 unsigned int db_pitch; 340 unsigned int db_aligned_height; 341 unsigned int db_tiling_mode; 342 unsigned int db_swizzle_mode; 343 unsigned int db_array_mode; 344 unsigned int db_field_mode; 345 unsigned int db_surf_tile_config; 346 347 unsigned int dt_pitch; 348 unsigned int dt_uv_pitch; 349 unsigned int dt_tiling_mode; 350 unsigned int dt_swizzle_mode; 351 unsigned int dt_array_mode; 352 unsigned int dt_field_mode; 353 unsigned int dt_out_format; 354 unsigned int dt_surf_tile_config; 355 unsigned int dt_uv_surf_tile_config; 356 unsigned int dt_luma_top_offset; 357 unsigned int dt_luma_bottom_offset; 358 unsigned int dt_chroma_top_offset; 359 unsigned int dt_chroma_bottom_offset; 360 unsigned int dt_chromaV_top_offset; 361 unsigned int dt_chromaV_bottom_offset; 362 363 unsigned char dpbRefArraySlice[16]; 364 unsigned char dpbCurArraySlice; 365 unsigned char dpbReserved[3]; 366 } rvcn_dec_message_decode_t; 367 368 typedef struct rvcn_dec_message_drm_s { 369 unsigned int drm_key[4]; 370 unsigned int drm_counter[4]; 371 unsigned int drm_wrapped_key[4]; 372 unsigned int drm_offset; 373 unsigned int drm_cmd; 374 unsigned int drm_cntl; 375 unsigned int drm_reserved; 376 } rvcn_dec_message_drm_t; 377 378 typedef struct { 379 unsigned short viewOrderIndex; 380 unsigned short viewId; 381 unsigned short numOfAnchorRefsInL0; 382 unsigned short viewIdOfAnchorRefsInL0[15]; 383 unsigned short numOfAnchorRefsInL1; 384 unsigned short viewIdOfAnchorRefsInL1[15]; 385 unsigned short numOfNonAnchorRefsInL0; 386 unsigned short viewIdOfNonAnchorRefsInL0[15]; 387 unsigned short numOfNonAnchorRefsInL1; 388 unsigned short viewIdOfNonAnchorRefsInL1[15]; 389 } radeon_mvcElement_t; 390 391 typedef struct rvcn_dec_message_avc_s { 392 unsigned int profile; 393 unsigned int level; 394 395 unsigned int sps_info_flags; 396 unsigned int pps_info_flags; 397 unsigned char chroma_format; 398 unsigned char bit_depth_luma_minus8; 399 unsigned char bit_depth_chroma_minus8; 400 unsigned char log2_max_frame_num_minus4; 401 402 unsigned char pic_order_cnt_type; 403 unsigned char log2_max_pic_order_cnt_lsb_minus4; 404 unsigned char num_ref_frames; 405 unsigned char reserved_8bit; 406 407 signed char pic_init_qp_minus26; 408 signed char pic_init_qs_minus26; 409 signed char chroma_qp_index_offset; 410 signed char second_chroma_qp_index_offset; 411 412 unsigned char num_slice_groups_minus1; 413 unsigned char slice_group_map_type; 414 unsigned char num_ref_idx_l0_active_minus1; 415 unsigned char num_ref_idx_l1_active_minus1; 416 417 unsigned short slice_group_change_rate_minus1; 418 unsigned short reserved_16bit_1; 419 420 unsigned char scaling_list_4x4[6][16]; 421 unsigned char scaling_list_8x8[2][64]; 422 423 unsigned int frame_num; 424 unsigned int frame_num_list[16]; 425 int curr_field_order_cnt_list[2]; 426 int field_order_cnt_list[16][2]; 427 428 unsigned int decoded_pic_idx; 429 unsigned int curr_pic_ref_frame_num; 430 unsigned char ref_frame_list[16]; 431 432 unsigned int reserved[122]; 433 434 struct { 435 unsigned int numViews; 436 unsigned int viewId0; 437 radeon_mvcElement_t mvcElements[1]; 438 } mvc; 439 440 } rvcn_dec_message_avc_t; 441 442 typedef struct rvcn_dec_message_vc1_s { 443 unsigned int profile; 444 unsigned int level; 445 unsigned int sps_info_flags; 446 unsigned int pps_info_flags; 447 unsigned int pic_structure; 448 unsigned int chroma_format; 449 unsigned short decoded_pic_idx; 450 unsigned short deblocked_pic_idx; 451 unsigned short forward_ref_idx; 452 unsigned short backward_ref_idx; 453 unsigned int cached_frame_flag; 454 } rvcn_dec_message_vc1_t; 455 456 typedef struct rvcn_dec_message_mpeg2_vld_s { 457 unsigned int decoded_pic_idx; 458 unsigned int forward_ref_pic_idx; 459 unsigned int backward_ref_pic_idx; 460 461 unsigned char load_intra_quantiser_matrix; 462 unsigned char load_nonintra_quantiser_matrix; 463 unsigned char reserved_quantiser_alignement[2]; 464 unsigned char intra_quantiser_matrix[64]; 465 unsigned char nonintra_quantiser_matrix[64]; 466 467 unsigned char profile_and_level_indication; 468 unsigned char chroma_format; 469 470 unsigned char picture_coding_type; 471 472 unsigned char reserved_1; 473 474 unsigned char f_code[2][2]; 475 unsigned char intra_dc_precision; 476 unsigned char pic_structure; 477 unsigned char top_field_first; 478 unsigned char frame_pred_frame_dct; 479 unsigned char concealment_motion_vectors; 480 unsigned char q_scale_type; 481 unsigned char intra_vlc_format; 482 unsigned char alternate_scan; 483 } rvcn_dec_message_mpeg2_vld_t; 484 485 typedef struct rvcn_dec_message_mpeg4_asp_vld_s { 486 unsigned int decoded_pic_idx; 487 unsigned int forward_ref_pic_idx; 488 unsigned int backward_ref_pic_idx; 489 490 unsigned int variant_type; 491 unsigned char profile_and_level_indication; 492 493 unsigned char video_object_layer_verid; 494 unsigned char video_object_layer_shape; 495 496 unsigned char reserved_1; 497 498 unsigned short video_object_layer_width; 499 unsigned short video_object_layer_height; 500 501 unsigned short vop_time_increment_resolution; 502 503 unsigned short reserved_2; 504 505 struct { 506 unsigned int short_video_header : 1; 507 unsigned int obmc_disable : 1; 508 unsigned int interlaced : 1; 509 unsigned int load_intra_quant_mat : 1; 510 unsigned int load_nonintra_quant_mat : 1; 511 unsigned int quarter_sample : 1; 512 unsigned int complexity_estimation_disable : 1; 513 unsigned int resync_marker_disable : 1; 514 unsigned int data_partitioned : 1; 515 unsigned int reversible_vlc : 1; 516 unsigned int newpred_enable : 1; 517 unsigned int reduced_resolution_vop_enable : 1; 518 unsigned int scalability : 1; 519 unsigned int is_object_layer_identifier : 1; 520 unsigned int fixed_vop_rate : 1; 521 unsigned int newpred_segment_type : 1; 522 unsigned int reserved_bits : 16; 523 }; 524 525 unsigned char quant_type; 526 unsigned char reserved_3[3]; 527 unsigned char intra_quant_mat[64]; 528 unsigned char nonintra_quant_mat[64]; 529 530 struct { 531 unsigned char sprite_enable; 532 533 unsigned char reserved_4[3]; 534 535 unsigned short sprite_width; 536 unsigned short sprite_height; 537 short sprite_left_coordinate; 538 short sprite_top_coordinate; 539 540 unsigned char no_of_sprite_warping_points; 541 unsigned char sprite_warping_accuracy; 542 unsigned char sprite_brightness_change; 543 unsigned char low_latency_sprite_enable; 544 } sprite_config; 545 546 struct { 547 struct { 548 unsigned int check_skip : 1; 549 unsigned int switch_rounding : 1; 550 unsigned int t311 : 1; 551 unsigned int reserved_bits : 29; 552 }; 553 554 unsigned char vol_mode; 555 556 unsigned char reserved_5[3]; 557 } divx_311_config; 558 559 struct { 560 unsigned char vop_data_present; 561 unsigned char vop_coding_type; 562 unsigned char vop_quant; 563 unsigned char vop_coded; 564 unsigned char vop_rounding_type; 565 unsigned char intra_dc_vlc_thr; 566 unsigned char top_field_first; 567 unsigned char alternate_vertical_scan_flag; 568 unsigned char vop_fcode_forward; 569 unsigned char vop_fcode_backward; 570 unsigned int TRB[2]; 571 unsigned int TRD[2]; 572 } vop; 573 574 } rvcn_dec_message_mpeg4_asp_vld_t; 575 576 typedef struct rvcn_dec_message_hevc_s { 577 unsigned int sps_info_flags; 578 unsigned int pps_info_flags; 579 unsigned char chroma_format; 580 unsigned char bit_depth_luma_minus8; 581 unsigned char bit_depth_chroma_minus8; 582 unsigned char log2_max_pic_order_cnt_lsb_minus4; 583 584 unsigned char sps_max_dec_pic_buffering_minus1; 585 unsigned char log2_min_luma_coding_block_size_minus3; 586 unsigned char log2_diff_max_min_luma_coding_block_size; 587 unsigned char log2_min_transform_block_size_minus2; 588 589 unsigned char log2_diff_max_min_transform_block_size; 590 unsigned char max_transform_hierarchy_depth_inter; 591 unsigned char max_transform_hierarchy_depth_intra; 592 unsigned char pcm_sample_bit_depth_luma_minus1; 593 594 unsigned char pcm_sample_bit_depth_chroma_minus1; 595 unsigned char log2_min_pcm_luma_coding_block_size_minus3; 596 unsigned char log2_diff_max_min_pcm_luma_coding_block_size; 597 unsigned char num_extra_slice_header_bits; 598 599 unsigned char num_short_term_ref_pic_sets; 600 unsigned char num_long_term_ref_pic_sps; 601 unsigned char num_ref_idx_l0_default_active_minus1; 602 unsigned char num_ref_idx_l1_default_active_minus1; 603 604 signed char pps_cb_qp_offset; 605 signed char pps_cr_qp_offset; 606 signed char pps_beta_offset_div2; 607 signed char pps_tc_offset_div2; 608 609 unsigned char diff_cu_qp_delta_depth; 610 unsigned char num_tile_columns_minus1; 611 unsigned char num_tile_rows_minus1; 612 unsigned char log2_parallel_merge_level_minus2; 613 614 unsigned short column_width_minus1[19]; 615 unsigned short row_height_minus1[21]; 616 617 signed char init_qp_minus26; 618 unsigned char num_delta_pocs_ref_rps_idx; 619 unsigned char curr_idx; 620 unsigned char reserved[1]; 621 int curr_poc; 622 unsigned char ref_pic_list[16]; 623 int poc_list[16]; 624 unsigned char ref_pic_set_st_curr_before[8]; 625 unsigned char ref_pic_set_st_curr_after[8]; 626 unsigned char ref_pic_set_lt_curr[8]; 627 628 unsigned char ucScalingListDCCoefSizeID2[6]; 629 unsigned char ucScalingListDCCoefSizeID3[2]; 630 631 unsigned char highestTid; 632 unsigned char isNonRef; 633 634 unsigned char p010_mode; 635 unsigned char msb_mode; 636 unsigned char luma_10to8; 637 unsigned char chroma_10to8; 638 639 unsigned char hevc_reserved[2]; 640 641 unsigned char direct_reflist[2][15]; 642 } rvcn_dec_message_hevc_t; 643 644 typedef struct rvcn_dec_message_vp9_s { 645 unsigned int frame_header_flags; 646 647 unsigned char frame_context_idx; 648 unsigned char reset_frame_context; 649 650 unsigned char curr_pic_idx; 651 unsigned char interp_filter; 652 653 unsigned char filter_level; 654 unsigned char sharpness_level; 655 unsigned char lf_adj_level[8][4][2]; 656 unsigned char base_qindex; 657 signed char y_dc_delta_q; 658 signed char uv_ac_delta_q; 659 signed char uv_dc_delta_q; 660 661 unsigned char log2_tile_cols; 662 unsigned char log2_tile_rows; 663 unsigned char tx_mode; 664 unsigned char reference_mode; 665 unsigned char chroma_format; 666 667 unsigned char ref_frame_map[8]; 668 669 unsigned char frame_refs[3]; 670 unsigned char ref_frame_sign_bias[3]; 671 unsigned char frame_to_show; 672 unsigned char bit_depth_luma_minus8; 673 unsigned char bit_depth_chroma_minus8; 674 675 unsigned char p010_mode; 676 unsigned char msb_mode; 677 unsigned char luma_10to8; 678 unsigned char chroma_10to8; 679 680 unsigned int vp9_frame_size; 681 unsigned int compressed_header_size; 682 unsigned int uncompressed_header_size; 683 } rvcn_dec_message_vp9_t; 684 685 typedef struct rvcn_dec_feature_index_s { 686 unsigned int feature_id; 687 unsigned int offset; 688 unsigned int size; 689 unsigned int filled; 690 } rvcn_dec_feature_index_t; 691 692 typedef struct rvcn_dec_feedback_header_s { 693 unsigned int header_size; 694 unsigned int total_size; 695 unsigned int num_buffers; 696 unsigned int status_report_feedback_number; 697 unsigned int status; 698 unsigned int value; 699 unsigned int errorBits; 700 rvcn_dec_feature_index_t index[1]; 701 } rvcn_dec_feedback_header_t; 702 703 typedef struct rvcn_dec_feedback_profiling_s { 704 unsigned int size; 705 706 unsigned int decodingTime; 707 unsigned int decodePlusOverhead; 708 unsigned int masterTimerHits; 709 unsigned int uvdLBSIREWaitCount; 710 711 unsigned int avgMPCMemLatency; 712 unsigned int maxMPCMemLatency; 713 unsigned int uvdMPCLumaHits; 714 unsigned int uvdMPCLumaHitPend; 715 unsigned int uvdMPCLumaSearch; 716 unsigned int uvdMPCChromaHits; 717 unsigned int uvdMPCChromaHitPend; 718 unsigned int uvdMPCChromaSearch; 719 720 unsigned int uvdLMIPerfCountLo; 721 unsigned int uvdLMIPerfCountHi; 722 unsigned int uvdLMIAvgLatCntrEnvHit; 723 unsigned int uvdLMILatCntr; 724 725 unsigned int frameCRC0; 726 unsigned int frameCRC1; 727 unsigned int frameCRC2; 728 unsigned int frameCRC3; 729 730 unsigned int uvdLMIPerfMonCtrl; 731 unsigned int uvdLMILatCtrl; 732 unsigned int uvdMPCCntl; 733 unsigned int reserved0[4]; 734 unsigned int decoderID; 735 unsigned int codec; 736 737 unsigned int dmaHwCrc32Enable; 738 unsigned int dmaHwCrc32Value; 739 unsigned int dmaHwCrc32Value2; 740 } rvcn_dec_feedback_profiling_t; 741 742 typedef struct rvcn_dec_vp9_nmv_ctx_mask_s { 743 unsigned short classes_mask[2]; 744 unsigned short bits_mask[2]; 745 unsigned char joints_mask; 746 unsigned char sign_mask[2]; 747 unsigned char class0_mask[2]; 748 unsigned char class0_fp_mask[2]; 749 unsigned char fp_mask[2]; 750 unsigned char class0_hp_mask[2]; 751 unsigned char hp_mask[2]; 752 unsigned char reserve[11]; 753 } rvcn_dec_vp9_nmv_ctx_mask_t; 754 755 typedef struct rvcn_dec_vp9_nmv_component_s { 756 unsigned char sign; 757 unsigned char classes[10]; 758 unsigned char class0[1]; 759 unsigned char bits[10]; 760 unsigned char class0_fp[2][3]; 761 unsigned char fp[3]; 762 unsigned char class0_hp; 763 unsigned char hp; 764 } rvcn_dec_vp9_nmv_component_t; 765 766 typedef struct rvcn_dec_vp9_probs_s { 767 rvcn_dec_vp9_nmv_ctx_mask_t nmvc_mask; 768 unsigned char coef_probs[4][2][2][6][6][3]; 769 unsigned char y_mode_prob[4][9]; 770 unsigned char uv_mode_prob[10][9]; 771 unsigned char single_ref_prob[5][2]; 772 unsigned char switchable_interp_prob[4][2]; 773 unsigned char partition_prob[16][3]; 774 unsigned char inter_mode_probs[7][3]; 775 unsigned char mbskip_probs[3]; 776 unsigned char intra_inter_prob[4]; 777 unsigned char comp_inter_prob[5]; 778 unsigned char comp_ref_prob[5]; 779 unsigned char tx_probs_32x32[2][3]; 780 unsigned char tx_probs_16x16[2][2]; 781 unsigned char tx_probs_8x8[2][1]; 782 unsigned char mv_joints[3]; 783 rvcn_dec_vp9_nmv_component_t mv_comps[2]; 784 } rvcn_dec_vp9_probs_t; 785 786 typedef struct rvcn_dec_vp9_probs_segment_s { 787 union { 788 rvcn_dec_vp9_probs_t probs; 789 unsigned char probs_data[RDECODE_VP9_PROBS_DATA_SIZE]; 790 }; 791 792 union { 793 struct { 794 unsigned int feature_data[8]; 795 unsigned char tree_probs[7]; 796 unsigned char pred_probs[3]; 797 unsigned char abs_delta; 798 unsigned char feature_mask[8]; 799 } seg; 800 unsigned char segment_data[256]; 801 }; 802 } rvcn_dec_vp9_probs_segment_t; 803 804 struct jpeg_params { 805 unsigned bsd_size; 806 unsigned dt_pitch; 807 unsigned dt_uv_pitch; 808 unsigned dt_luma_top_offset; 809 unsigned dt_chroma_top_offset; 810 bool direct_reg; 811 }; 812 813 struct radeon_decoder { 814 struct pipe_video_codec base; 815 816 unsigned stream_handle; 817 unsigned stream_type; 818 unsigned frame_number; 819 820 struct pipe_screen *screen; 821 struct radeon_winsys *ws; 822 struct radeon_cmdbuf *cs; 823 824 void *msg; 825 uint32_t *fb; 826 uint8_t *it; 827 uint8_t *probs; 828 void *bs_ptr; 829 830 struct rvid_buffer msg_fb_it_probs_buffers[NUM_BUFFERS]; 831 struct rvid_buffer bs_buffers[NUM_BUFFERS]; 832 struct rvid_buffer dpb; 833 struct rvid_buffer ctx; 834 struct rvid_buffer sessionctx; 835 836 unsigned bs_size; 837 unsigned cur_buffer; 838 void *render_pic_list[32]; 839 bool show_frame; 840 unsigned ref_idx; 841 struct { 842 unsigned data0; 843 unsigned data1; 844 unsigned cmd; 845 unsigned cntl; 846 } reg; 847 struct jpeg_params jpg; 848 void (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target, 849 struct pipe_picture_desc *picture); 850 }; 851 852 void send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target, 853 struct pipe_picture_desc *picture); 854 855 void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target, 856 struct pipe_picture_desc *picture); 857 858 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, 859 const struct pipe_video_codec *templat); 860 861 #endif 862