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/external/ethtool/
Ddsa.c8 #define REG(_reg, _name, _val) \ macro
37 REG(reg, "Port Status", val); in dsa_mv88e6161()
56 REG(reg, "PCS Control", val); in dsa_mv88e6161()
70 REG(reg, "Jamming Control", val); in dsa_mv88e6161()
73 REG(reg, "Switch Identifier", val); in dsa_mv88e6161()
76 REG(reg, "Port Control", val); in dsa_mv88e6161()
113 REG(reg, "Port Control 1", val); in dsa_mv88e6161()
120 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6161()
125 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6161()
131 REG(reg, "Port Control 2", val); in dsa_mv88e6161()
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dselectcc-03.ll8 ; CHECK: ipm [[REG:%r[0-5]]]
9 ; CHECK-NEXT: afi [[REG]], -268435456
10 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
11 ; CHECK-NEXT: srag %r2, [[REG]], 63
21 ; CHECK: ipm [[REG:%r[0-5]]]
22 ; CHECK-NEXT: xilf [[REG]], 268435456
23 ; CHECK-NEXT: afi [[REG]], -268435456
24 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
25 ; CHECK-NEXT: srag %r2, [[REG]], 63
35 ; CHECK: ipm [[REG:%r[0-5]]]
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dselectcc-03.ll8 ; CHECK: ipm [[REG:%r[0-5]]]
9 ; CHECK-NEXT: afi [[REG]], -268435456
10 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
11 ; CHECK-NEXT: srag %r2, [[REG]], 63
21 ; CHECK: ipm [[REG:%r[0-5]]]
22 ; CHECK-NEXT: xilf [[REG]], 268435456
23 ; CHECK-NEXT: afi [[REG]], -268435456
24 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
25 ; CHECK-NEXT: srag %r2, [[REG]], 63
35 ; CHECK: ipm [[REG:%r[0-5]]]
[all …]
Dsetcc-04.ll8 ; CHECK: ipm [[REG:%r[0-5]]]
9 ; CHECK-NEXT: afi [[REG]], -268435456
10 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
20 ; CHECK: ipm [[REG:%r[0-5]]]
21 ; CHECK-NEXT: xilf [[REG]], 268435456
22 ; CHECK-NEXT: afi [[REG]], -268435456
23 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
33 ; CHECK: ipm [[REG:%r[0-5]]]
34 ; CHECK-NEXT: afi [[REG]], -536870912
35 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
[all …]
/external/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll5 ; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
7 ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
8 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
9 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
10 ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
20 ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
22 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
23 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll5 ; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
7 ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
8 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
9 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
10 ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
20 ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
22 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
23 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
[all …]
Darm-position-independence.ll33 ; ARM_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
34 ; ARM_RW_ABS: movt r[[REG]], :upper16:a
35 ; ARM_RW_ABS: ldr r0, [r[[REG]]]
37 ; ARM_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
38 ; ARM_RW_SB: movt r[[REG]], :upper16:a(sbrel)
39 ; ARM_RW_SB: ldr r0, [r9, r[[REG]]]
41 ; NO_MOVT_ARM_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
42 ; NO_MOVT_ARM_RW_SB: ldr r0, [r9, r[[REG]]]
44 ; THUMB2_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
45 ; THUMB2_RW_ABS: movt r[[REG]], :upper16:a
[all …]
/external/arm-trusted-firmware/drivers/arm/gic/v3/
Dgicv3_private.h28 #define BIT_NUM(REG, id) \ argument
29 ((id) & ((1U << REG##R_SHIFT) - 1U))
37 #define GICD_OFFSET_8(REG, id) \ argument
39 GICD_##REG##R + (uintptr_t)(id) : \
40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
42 #define GICD_OFFSET(REG, id) \ argument
44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
46 REG##R_SHIFT) << 2))
48 #define GICD_OFFSET_64(REG, id) \ argument
[all …]
/external/elfutils/libcpu/
Dbpf_disasm.c55 #define REG(N) "r%" #N "$d" macro
56 #define REGU(N) "(u32)" REG(N)
57 #define REGS(N) "(s64)" REG(N)
65 #define A32(O, S) REG(1) " = " REGU(1) " " #O " " S
66 #define A64(O, S) REG(1) " " #O "= " S
68 #define LOAD(T) REG(1) " = *(" #T " *)(" REG(2) OFF(3) ")"
69 #define STORE(T, S) "*(" #T " *)(" REG(1) OFF(3) ") = " S
70 #define XADD(T, S) "lock *(" #T " *)(" REG(1) OFF(3) ") += " S
141 code_fmt = REG(1) " = %2$#" PRIx64; in bpf_disasm()
144 code_fmt = REG(1) " = map_fd(%2$#" PRIx64 ")"; in bpf_disasm()
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dasm-mismatched-types.ll9 ; __asm__ __volatile__("# REG: %0" : : "r" (reg)); }
12 ; CHECK: # REG: %r8d
14 call void asm sideeffect "# REG: $0", "{r8}"(i32 %p)
19 ; CHECK: # REG: %r8d
21 call void asm sideeffect "# REG: $0", "{r8}"(float %p)
26 ; CHECK: # REG: %r9w
28 call void asm sideeffect "# REG: $0", "{r9}"(i16 %p)
33 ; CHECK: # REG: %bpl
35 call void asm sideeffect "# REG: $0", "{rbp}"(i8 %p)
40 ; CHECK: # REG: %r15w
[all …]
/external/llvm/test/CodeGen/X86/
Dasm-mismatched-types.ll9 ; __asm__ __volatile__("# REG: %0" : : "r" (reg)); }
12 ; CHECK: # REG: %r8d
14 call void asm sideeffect "# REG: $0", "{r8}"(i32 %p)
19 ; CHECK: # REG: %r8d
21 call void asm sideeffect "# REG: $0", "{r8}"(float %p)
26 ; CHECK: # REG: %r9w
28 call void asm sideeffect "# REG: $0", "{r9}"(i16 %p)
33 ; CHECK: # REG: %bpl
35 call void asm sideeffect "# REG: $0", "{rbp}"(i8 %p)
40 ; CHECK: # REG: %r15w
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfloat-to-int.ll17 ; CHECK: fctidz [[REG:[0-9]+]], 1
18 ; CHECK: stfd [[REG]],
23 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
24 ; CHECK-VSX: stfd [[REG]],
29 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
30 ; CHECK-P9: stfd [[REG]],
40 ; CHECK: fctidz [[REG:[0-9]+]], 1
41 ; CHECK: stfd [[REG]],
46 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
47 ; CHECK-VSX: stfd [[REG]],
[all …]
Di64-to-float.ll17 ; CHECK: lfd [[REG:[0-9]+]],
18 ; CHECK: fcfids 1, [[REG]]
23 ; CHECK-VSX: lfd [[REG:[0-9]+]],
24 ; CHECK-VSX: fcfids 1, [[REG]]
29 ; CHECK-P9: lfd [[REG:[0-9]+]],
30 ; CHECK-P9: xscvsxdsp 1, [[REG]]
41 ; CHECK: lfd [[REG:[0-9]+]],
42 ; CHECK: fcfid 1, [[REG]]
47 ; CHECK-VSX: lfd [[REG:[0-9]+]],
48 ; CHECK-VSX: xscvsxddp 1, [[REG]]
[all …]
Dvsx.ll8 ; RUN: -check-prefix=CHECK-REG %s
24 ; CHECK-REG-LABEL: test1:
25 ; CHECK-REG: # %bb.0: # %entry
26 ; CHECK-REG-NEXT: xsmuldp f1, f1, f2
27 ; CHECK-REG-NEXT: blr
51 ; CHECK-REG-LABEL: test2:
52 ; CHECK-REG: # %bb.0: # %entry
53 ; CHECK-REG-NEXT: xsdivdp f1, f1, f2
54 ; CHECK-REG-NEXT: blr
78 ; CHECK-REG-LABEL: test3:
[all …]
Di32-to-float.ll14 ; CHECK: extsw [[REG:[0-9]+]], 3
15 ; CHECK: std [[REG]],
23 ; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
24 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
30 ; CHECK-A2: lfiwax [[REG:[0-9]+]],
31 ; CHECK-A2: fcfids 1, [[REG]]
36 ; CHECK-VSX: lfiwax [[REG:[0-9]+]],
37 ; CHECK-VSX: fcfids 1, [[REG]]
47 ; CHECK: extsw [[REG:[0-9]+]], 3
48 ; CHECK: std [[REG]],
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfast-isel-runtime-libcall.ll8 ; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE
9 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}}
10 ; LARGE-NEXT: blr [[REG]]
19 ; LARGE: adrp [[REG:x[0-9]+]], _fmod@GOTPAGE
20 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod@GOTPAGEOFF{{\]}}
21 ; LARGE-NEXT: blr [[REG]]
30 ; LARGE: adrp [[REG:x[0-9]+]], _sinf@GOTPAGE
31 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _sinf@GOTPAGEOFF{{\]}}
32 ; LARGE-NEXT: blr [[REG]]
41 ; LARGE: adrp [[REG:x[0-9]+]], _sin@GOTPAGE
[all …]
Darm64-shifted-sext.ll8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
45 ; CHECK: sxtb [[REG]], [[REG]]
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
[all …]
Darm64-scvt.ll49 ; CHECK: ldr [[REG:w[0-9]+]], [x0]
50 ; CHECK: scvtf d0, [[REG]]
75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
76 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
89 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
102 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
116 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfast-isel-runtime-libcall.ll8 ; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE
9 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}}
10 ; LARGE-NEXT: blr [[REG]]
19 ; LARGE: adrp [[REG:x[0-9]+]], _fmod@GOTPAGE
20 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod@GOTPAGEOFF{{\]}}
21 ; LARGE-NEXT: blr [[REG]]
30 ; LARGE: adrp [[REG:x[0-9]+]], _sinf@GOTPAGE
31 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _sinf@GOTPAGEOFF{{\]}}
32 ; LARGE-NEXT: blr [[REG]]
41 ; LARGE: adrp [[REG:x[0-9]+]], _sin@GOTPAGE
[all …]
Darm64-shifted-sext.ll8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
45 ; CHECK: sxtb [[REG]], [[REG]]
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
[all …]
Dtagged-globals-pic.ll26 ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
27 ; CHECK-PIC: ldr x0, {{\[}}[[REG]], :got_lo12:global]
35 ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
36 ; CHECK-SELECTIONDAGISEL: ldr w0, {{\[}}[[REG]], :lo12:global{{\]}}
40 ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
41 ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296
42 ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
43 ; CHECK-GLOBALISEL: ldr w0, {{\[}}[[REG]]{{\]}}
47 ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
48 ; CHECK-PIC: ldr [[REG]], {{\[}}[[REG]], :got_lo12:global]
[all …]
Darm64-scvt.ll49 ; CHECK: ldr [[REG:w[0-9]+]], [x0]
50 ; CHECK: scvtf d0, [[REG]]
75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
76 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
89 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
102 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
116 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dfloat-to-int.ll12 ; CHECK: fctidz [[REG:[0-9]+]], 1
13 ; CHECK: stfd [[REG]],
18 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
19 ; CHECK-VSX: stxsdx [[REG]],
29 ; CHECK: fctidz [[REG:[0-9]+]], 1
30 ; CHECK: stfd [[REG]],
35 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
36 ; CHECK-VSX: stxsdx [[REG]],
46 ; CHECK: fctiduz [[REG:[0-9]+]], 1
47 ; CHECK: stfd [[REG]],
[all …]
Di32-to-float.ll14 ; CHECK: extsw [[REG:[0-9]+]], 3
15 ; CHECK: std [[REG]],
23 ; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
24 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
30 ; CHECK-A2: lfiwax [[REG:[0-9]+]],
31 ; CHECK-A2: fcfids 1, [[REG]]
36 ; CHECK-VSX: lfiwax [[REG:[0-9]+]],
37 ; CHECK-VSX: fcfids 1, [[REG]]
47 ; CHECK: extsw [[REG:[0-9]+]], 3
48 ; CHECK: std [[REG]],
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dimm.ll34 ; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
35 ; CHECK: buffer_store_dword [[REG]]
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
43 ; CHECK: buffer_store_dword [[REG]]
50 ; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
51 ; CHECK: buffer_store_dword [[REG]]
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
59 ; CHECK: buffer_store_dword [[REG]]
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
67 ; CHECK: buffer_store_dword [[REG]]
[all …]

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