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Searched refs:REGS (Results 1 – 8 of 8) sorted by relevance

/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/X86/
Dlsr-insns-1.ll3 …N: opt < %s -loop-reduce -mtriple=x86_64 -lsr-insns-cost=false -S | FileCheck %s -check-prefix=REGS
50 ; REGS-LABEL: @foo(
51 ; REGS-NEXT: entry:
52 ; REGS-NEXT: br label [[FOR_BODY:%.*]]
53 ; REGS: for.cond.cleanup:
54 ; REGS-NEXT: ret void
55 ; REGS: for.body:
56 ; REGS-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR…
57 ; REGS-NEXT: [[SCEVGEP2:%.*]] = getelementptr i32, i32* [[X:%.*]], i64 [[INDVARS_IV]]
58 ; REGS-NEXT: [[TMP:%.*]] = load i32, i32* [[SCEVGEP2]], align 4
[all …]
Dlsr-insns-2.ll2 …uce -mtriple=x86_64-- -lsr-insns-cost=false -S | FileCheck %s -check-prefix=BOTH -check-prefix=REGS
13 ; REGS: %lsr.iv4 = phi
14 ; REGS: %lsr.iv2 = phi
15 ; REGS: %lsr.iv1 = phi
16 ; REGS: getelementptr i32, i32* %lsr.iv1, i64 1
17 ; REGS: getelementptr i32, i32* %lsr.iv2, i64 1
18 ; REGS: getelementptr i32, i32* %lsr.iv4, i64 1
/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dmultivalue.ll2 …plicit-locals -wasm-keep-registers -mattr=+multivalue,+tail-call | FileCheck %s --check-prefix REGS
41 ; REGS: call $drop=, $drop=, pair_const{{$}}
51 ; REGS: call $push{{[0-9]+}}=, $push{{[0-9]+}}=, pair_const{{$}}
62 ; REGS: call_indirect $push{{[0-9]+}}=, $push{{[0-9]+}}=, $0{{$}}
72 ; REGS: return_call pair_const{{$}}
83 ; REGS: call $push{{[0-9]+}}=, $drop=, pair_const{{$}}
98 ; REGS: call $drop=, $0=, pair_const{{$}}
111 ; REGS: call $push{{[0-9]+}}=, $drop=, pair_const{{$}}
128 ; REGS: call $drop=, $0=, pair_const{{$}}
144 ; REGS: call $push{{[0-9]+}}=, $0=, pair_const{{$}}
[all …]
/external/elfutils/libcpu/
Dbpf_disasm.c57 #define REGS(N) "(s64)" REG(N) macro
344 code_fmt = J64(REGS(1), >, IMMS(2)); in bpf_disasm()
347 code_fmt = J64(REGS(1), >=, IMMS(2)); in bpf_disasm()
356 code_fmt = J64(REGS(1), <, IMMS(2)); in bpf_disasm()
359 code_fmt = J64(REGS(1), <=, IMMS(2)); in bpf_disasm()
378 code_fmt = J64(REGS(1), >, REGS(2)); in bpf_disasm()
381 code_fmt = J64(REGS(1), >=, REGS(2)); in bpf_disasm()
390 code_fmt = J64(REGS(1), <, REGS(2)); in bpf_disasm()
393 code_fmt = J64(REGS(1), <=, REGS(2)); in bpf_disasm()
/external/libpcap/msdos/
Dpktdrvr.c320 union REGS r; in PktInterrupt()
1285 union REGS r; in dpmi_get_real_vector()
1295 union REGS r; in dpmi_real_malloc()
1309 union REGS r; in dpmi_real_free()
/external/crosvm/src/plugin/
Dvcpu.rs90 VcpuRequest_StateSet::REGS => VcpuRegs(vcpu.get_regs()?).as_slice().to_vec(), in get_vcpu_state()
103 VcpuRequest_StateSet::REGS => { in set_vcpu_state()
615 set_vcpu_state(vcpu, VcpuRequest_StateSet::REGS, resume.get_regs())?; in handle_request()
/external/crosvm/crosvm_plugin/src/
Dlib.rs1239 VcpuRequest_StateSet::REGS => { in set_state_from_cache()
1768 if let Err(e) = this.set_state_from_cache(VcpuRequest_StateSet::REGS) { in crosvm_vcpu_get_regs()
1777 let ret = this.get_state(VcpuRequest_StateSet::REGS, regs); in crosvm_vcpu_get_regs()
/external/crosvm/protos/src/
Dplugin.proto307 REGS = 0; enumerator