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Searched refs:REG_SOC_WMSK (Results 1 – 8 of 8) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c946 REG_SOC_WMSK | GRF_IOMUX_GPIO); in suspend_apio()
948 REG_SOC_WMSK | GRF_IOMUX_GPIO); in suspend_apio()
950 REG_SOC_WMSK | GRF_IOMUX_GPIO); in suspend_apio()
953 mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0); in suspend_apio()
954 mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0); in suspend_apio()
955 mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0); in suspend_apio()
966 REG_SOC_WMSK | GRF_IOMUX_GPIO); in suspend_apio()
968 REG_SOC_WMSK | GRF_IOMUX_GPIO); in suspend_apio()
971 mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0); in suspend_apio()
972 mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0); in suspend_apio()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c128 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
129 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
131 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in restore_pll()
132 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in restore_pll()
135 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in restore_pll()
199 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
202 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
211 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); in clk_gate_con_restore()
215 REG_SOC_WMSK | slp_data.cru_gate_con[i]); in clk_gate_con_restore()
291 pmu_slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK); in restore_pmu_rsthold()
[all …]
Dsoc.h51 #define REG_SOC_WMSK 0xffff0000 macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/
Dsecure.c139 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); in secure_sgrf_init()
141 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); in secure_sgrf_init()
143 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS); in secure_sgrf_init()
/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/
Dsoc.c140 slp_data.pll_mode | REG_SOC_WMSK); in clk_plls_resume()
157 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
166 REG_SOC_WMSK | slp_data.cru_gate_con[i]); in clk_gate_con_restore()
189 val = slp_data.cru_sel_con[i] | REG_SOC_WMSK; in clk_sel_con_restore()
Dsoc.h94 #define REG_SOC_WMSK 0xffff0000 macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c650 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
651 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
653 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
654 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
656 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
767 cru_clksel_con6 | REG_SOC_WMSK); in dmc_resume()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c356 cru_gate_save | REG_SOC_WMSK); in plat_rockchip_save_gpio()
375 REG_SOC_WMSK | store_grf_gpio[i]); in plat_rockchip_restore_gpio()
406 cru_gate_save | REG_SOC_WMSK); in plat_rockchip_restore_gpio()