Searched refs:REG_W (Results 1 – 3 of 3) sorted by relevance
| /external/igt-gpu-tools/lib/ |
| D | i915_3d.h | 303 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
415 i915_get_hardware_channel_val(REG_W(operand0), \
430 i915_get_hardware_channel_val(REG_W(operand1), \
445 i915_get_hardware_channel_val(REG_W(operand2), \
468 i915_get_hardware_channel_val(REG_W(operand0), \
483 i915_get_hardware_channel_val(REG_W(operand1), \
498 i915_get_hardware_channel_val(REG_W(operand2), \
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset…
42 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[REG_W]]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset…
42 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[REG_Y]]
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