Searched refs:REG_X (Results 1 – 4 of 4) sorted by relevance
| /external/igt-gpu-tools/lib/ |
| D | i915_3d.h | 300 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
421 i915_get_hardware_channel_val(REG_X(operand1), \
436 i915_get_hardware_channel_val(REG_X(operand2), \
459 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
474 i915_get_hardware_channel_val(REG_X(operand1), \
489 i915_get_hardware_channel_val(REG_X(operand2), \
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| /external/llvm/test/CodeGen/X86/ |
| D | divrem8_ext.ll | 30 ; CHECK: divb [[REG_X:%[a-z0-9]+]]
32 ; CHECK: addb [[REG_X]], %al
77 ; CHECK: idivb [[REG_X:%[a-z0-9]+]]
79 ; CHECK: addb [[REG_X]], %al
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 39 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
41 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
65 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
67 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 39 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
41 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
65 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
67 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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