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Searched refs:REV (Results 1 – 25 of 113) sorted by relevance

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/external/llvm-project/llvm/utils/crosstool/
Dcreate-snapshots.sh20 readonly REV="${1:-$(getLatestRevisionFromSVN)}"
25 echo "Running: svn export -r ${REV} ${module}; log in ${log}"
26 svn -q export -r ${REV} ${LLVM_PROJECT_SVN}/${module}/trunk \
30 local tarball="${module}-${REV}.tar.bz2"
/external/llvm/utils/crosstool/
Dcreate-snapshots.sh20 readonly REV="${1:-$(getLatestRevisionFromSVN)}"
25 echo "Running: svn export -r ${REV} ${module}; log in ${log}"
26 svn -q export -r ${REV} ${LLVM_PROJECT_SVN}/${module}/trunk \
30 local tarball="${module}-${REV}.tar.bz2"
/external/llvm-project/lld/test/ELF/linkerscript/
Dmulti-sections-constraint.s20 # RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=REV
22 # REV: Sections:
23 # REV-NEXT: Idx Name Size VMA Type
24 # REV: .aaa 00000010 0000000000001000 DATA
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-bitcast-bigendian.mir13 ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
14 ; CHECK: $x0 = COPY [[REV]]
/external/libwebsockets/win32port/zlib/
Dcrc32.c56 # define REV(w) ((((w)>>24)&0xff)+(((w)>>8)&0xff00)+ \ macro
141 crc_table[4][n] = REV(c); in make_crc_table()
145 crc_table[k + 4][n] = REV(c); in make_crc_table()
312 c = REV((u4)crc);
334 return (unsigned long)(REV(c));
/external/llvm/docs/
DBigEndianNEON.rst78 …DR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can simulate either typ…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
133 … to avoid alignment faults (the result of the ``LD1`` would then need to be reversed with ``REV``).
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
161 2. Create code generation patterns for bitconverts that create ``REV`` instructions.
188 …REV`` undoing the ``LD1`` of type ``X`` (converting the in-register representation to the same as …
202 It turns out that these ``REV`` pairs can, in almost all cases, be squashed together into a single …
/external/llvm-project/llvm/docs/
DBigEndianNEON.rst78 …DR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can simulate either typ…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
133 … to avoid alignment faults (the result of the ``LD1`` would then need to be reversed with ``REV``).
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
161 2. Create code generation patterns for bitconverts that create ``REV`` instructions.
188 …REV`` undoing the ``LD1`` of type ``X`` (converting the in-register representation to the same as …
202 It turns out that these ``REV`` pairs can, in almost all cases, be squashed together into a single …
/external/e2fsprogs/lib/ext2fs/
Dutf8n.h31 #define UNICODE_AGE(MAJ, MIN, REV) \ argument
34 ((unsigned int)(REV)))
Dnls_utf8.c38 #define UNICODE_AGE(MAJ, MIN, REV) \ argument
41 ((unsigned int)(REV)))
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dbswap.ll346 ; CHECK-NEXT: [[REV:%.*]] = call i16 @llvm.bswap.i16(i16 [[TRUNC]])
347 ; CHECK-NEXT: ret i16 [[REV]]
361 ; CHECK-NEXT: [[REV:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[TRUNC]])
362 ; CHECK-NEXT: ret <2 x i16> [[REV]]
376 ; CHECK-NEXT: [[REV:%.*]] = call i32 @llvm.bswap.i32(i32 [[TRUNC]])
377 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[REV]] to i64
397 ; CHECK-NEXT: [[REV:%.*]] = call i32 @llvm.bswap.i32(i32 [[TRUNC]])
398 ; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[REV]] to i16
419 ; CHECK-NEXT: [[REV:%.*]] = call i16 @llvm.bswap.i16(i16 [[TRUNC]])
420 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[REV]] to i64
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-rn-t32.json35 "Rev", // REV{<c>}{<q>} <Rd>, <Rm> ; T1
36 // REV{<c>}{<q>} <Rd>, <Rm> ; T2
Dcond-rd-rn-a32.json31 "Rev", // REV{<c>}{<q>} <Rd>, <Rm> ; A1
/external/libavc/encoder/
Dih264e_cabac.h55 #define REV(u4_input, u4_output) \ macro
/external/openssh/
Dbuildpkg.sh.in252 VERSION=$VERSION$REV
659 echo | pkgtrans -os ${FAKE_ROOT} ${START}/$PKGNAME-$VERSION$REV-$UNAME_S-$ARCH.pkg
670 echo | pkgtrans -os ${FAKE_ROOT} ${START}/$PKGNAME-$VERSION$REV-$UNAME_S-$ARCH.pkg
/external/f2fs-tools/lib/
Dnls_utf8.c36 #define UNICODE_AGE(MAJ, MIN, REV) \ argument
39 ((unsigned int)(REV)))
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleM4.td88 "t2(S|Q|SH|U|UQ|UH|QD)(ADD|ASX|SAX|SUB)", "t2USADA8", "(t|t2)REV")>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMScheduleM4.td88 "t2(S|Q|SH|U|UQ|UH|QD)(ADD|ASX|SAX|SUB)", "t2USADA8", "(t|t2)REV")>;
/external/mdnsresponder/mDNSShared/
DCommonServices.h1182 #define NumVersionBuild( MAJOR, MINOR, BUGFIX, STAGE, REV ) \ argument
1187 ( ( ( REV ) & 0xFF ) ) )
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt342 # REV/REV16/REVSH
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt342 # REV/REV16/REVSH
/external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/
Dvpaes-armv7.S1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
/external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/
Dvpaes-armv7.S1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
/external/boringssl/ios-arm/crypto/fipsmodule/
Dvpaes-armv7.S1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
/external/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7.S1023 @ cost of extra REV and VREV32 operations in little-endian ARM.
1123 @ cost of extra REV and VREV32 operations in little-endian ARM.
/external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/
Dvpaes-armv7.S1023 @ cost of extra REV and VREV32 operations in little-endian ARM.
1123 @ cost of extra REV and VREV32 operations in little-endian ARM.

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