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Searched refs:RH (Results 1 – 25 of 85) sorted by relevance

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/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp2122, i64* %RH
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp2122, i64* %RH
/external/llvm-project/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp2122, i64* %RH
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp2122, i64* %RH
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dmisched-fusion-addr.ll29 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
30 ; CHECK-NEXT: strh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}}
42 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
43 ; CHECK-NEXT: ldrh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}}
83 ; CHECK: adrp [[RH:x[0-9]+]], var_half
84 ; CHECK-NEXT: ldr {{h[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_half{{\]}}
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
27 store i64 %tmp2122, i64* %RH
Dadde.ll17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
32 store i64 %tmp2122, i64* %RH
/external/strace/
DChangeLog-CVS296 Fixes RH#471169 "format fcntl64() system calls for
361 Fixes RH#472053.
399 Fixes RH#470529.
463 Fixes RH#105371.
552 Fixes RH#455078.
571 Fixes RH#457291.
620 Fixes RH#448628.
634 Fixes RH#448629.
638 Fixes RH#455821.
682 Fixes RH#453438.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
509 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
539 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
547 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
552 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
DTargetLowering.cpp5738 SDValue LH, SDValue RL, SDValue RH) const { in expandMUL_LOHI()
5760 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
5761 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL_LOHI()
5827 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
5832 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
5833 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL_LOHI()
5845 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL_LOHI()
5847 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL_LOHI()
5862 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) in expandMUL_LOHI()
5888 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) in expandMUL_LOHI()
[all …]
DLegalizeIntegerTypes.cpp2910 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2912 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
2914 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); in ExpandIntRes_Logical()
2923 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
2925 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
2929 LL, LH, RL, RH)) in ExpandIntRes_MUL()
2986 DAG.getNode(ISD::MUL, dl, NVT, RH, LL), in ExpandIntRes_MUL()
3070 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
3072 GetExpandedInteger(RHS, RL, RH); in ExpandIntRes_MULFIX()
3078 LL, LH, RL, RH)) { in ExpandIntRes_MULFIX()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp525 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
528 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
542 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
547 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
550 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
555 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
DTargetLowering.cpp2982 SDValue RL, SDValue RH) const { in expandMUL()
2997 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL()
2998 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL()
3044 if (!LH.getNode() && !RH.getNode() && in expandMUL()
3052 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); in expandMUL()
3053 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL()
3065 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
3067 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
3074 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
3076 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
/external/icu/icu4c/source/data/coll/
Dcy.txt14 "&R<rh<<<Rh<<<RH"
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp510 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
513 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
543 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
548 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
551 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
556 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
DTargetLowering.cpp6025 SDValue LH, SDValue RL, SDValue RH) const { in expandMUL_LOHI()
6047 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
6048 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL_LOHI()
6114 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
6119 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
6120 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL_LOHI()
6132 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL_LOHI()
6134 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL_LOHI()
6149 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) in expandMUL_LOHI()
6175 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) in expandMUL_LOHI()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1614 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1618 RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1671 unsigned B, RegHalf &RH);
1701 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
1768 RH.Reg = Reg; in matchHalf()
1769 RH.Sub = Sub; in matchHalf()
1770 RH.Low = Low; in matchHalf()
1772 if (!HBS::getFinalVRegClass(RH, MRI)) in matchHalf()
1773 RH.Sub = 0; in matchHalf()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1699 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1701 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1754 unsigned B, RegHalf &RH);
1797 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
1864 RH.Reg = Reg; in matchHalf()
1865 RH.Sub = Sub; in matchHalf()
1866 RH.Low = Low; in matchHalf()
1868 if (!HBS::getFinalVRegClass(RH, MRI)) in matchHalf()
1869 RH.Sub = 0; in matchHalf()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1709 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1711 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1764 unsigned B, RegHalf &RH);
1807 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
1874 RH.Reg = Reg; in matchHalf()
1875 RH.Sub = Sub; in matchHalf()
1876 RH.Low = Low; in matchHalf()
1878 if (!HBS::getFinalVRegClass(RH, MRI)) in matchHalf()
1879 RH.Sub = 0; in matchHalf()
/external/cldr/tools/java/org/unicode/cldr/util/data/
DlocaleReplacements.txt91 territory deprecated RH ZW
/external/python/cpython2/Demo/tix/
DINSTALL.txt7 Tix.py has been written and tested on an Intel Pentium running RH Linux 5.2
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DLowerMatrixIntrinsics.cpp743 Value *RH = Builder.CreateExtractElement(Rhs.getColumn(J), K); in LowerMultiply() local
744 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat"); in LowerMultiply()
/external/icu/icu4c/source/data/translit/
DGrek_Latn.txt181 Ρ $rough ↔ RH ;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp676 SDValue LH, RH; in TryExpandADDWithMul() local
679 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
685 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
687 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp675 SDValue LH, RH; in TryExpandADDWithMul() local
678 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
684 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
686 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp701 SDValue LH, RH; in TryExpandADDWithMul() local
704 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
710 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
712 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/external/ImageMagick/PerlMagick/t/reference/filter/
DSigmoidalContrast.miff15 …�Cu�Jm�Lm�Hl�Aw�Nu�S[�BdZIe[Je[Je[JdZIg]Mf]Le[Ie]De]@d]C[T>DB.8=,8@0;B6NF3�RH�<>�2$�/�0!�2!�2 �1!…

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