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Searched refs:RIP (Results 1 – 25 of 103) sorted by relevance

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/external/scapy/scapy/layers/
Drip.py14 class RIP(Packet): class
30 class RIPEntry(RIP):
70 bind_layers( UDP, RIP, sport=520)
71 bind_layers( UDP, RIP, dport=520)
72 bind_layers( RIP, RIPEntry, )
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_x64.h51 uintptr_t RIP; member
74 static_assert(offsetof(marl_fiber_context, RIP) == MARL_REG_RIP,
Dosfiber_x64.c33 ctx->RIP = (uintptr_t)&marl_fiber_trampoline; in marl_fiber_set_target()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td148 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
345 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
346 // RIP isn't really a register and it can't be used anywhere except in an
350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
376 R8, R9, R11, RIP)>;
378 R8, R9, R10, R11, RIP)>;
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
406 // GR64_NOSP - GR64 registers except RSP (and RIP).
407 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
421 // In such cases, it is fine to use RIP as we are sure the 32 high
[all …]
DX86RegisterInfo.cpp51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
442 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid(); in getReservedRegs()
521 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.td188 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
417 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
418 // RIP isn't really a register and it can't be used anywhere except in an
421 // tests because of the inclusion of RIP in this register class.
424 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
450 R8, R9, R11, RIP, RSP)>;
453 RIP, RSP)>;
471 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
476 // GR64_NOSP - GR64 registers except RSP (and RIP).
477 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
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DX86RegisterInfo.cpp45 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
48 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
540 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs()
623 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
DX86SpeculativeLoadHardening.cpp1119 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1159 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1720 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && in tracePredStateThroughBlocksAndHarden()
1972 } else if (BaseMO.getReg() == X86::RIP || in hardenLoadAddr()
1984 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base") in hardenLoadAddr()
2503 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
2545 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
/external/llvm-project/llvm/lib/Target/X86/
DX86RegisterInfo.td188 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
427 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
428 // RIP isn't really a register and it can't be used anywhere except in an
431 // tests because of the inclusion of RIP in this register class.
434 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
460 R8, R9, R11, RIP, RSP)>;
463 RIP, RSP)>;
481 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
486 // GR64_NOSP - GR64 registers except RSP (and RIP).
487 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
[all …]
DX86RegisterInfo.cpp46 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
49 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
535 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs()
618 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
829 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
DX86SpeculativeExecutionSideEffectSuppression.cpp83 if (MO.isReg() && X86::RIP != MO.getReg()) in hasConstantAddressingMode()
DX86SpeculativeLoadHardening.cpp1125 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1165 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1345 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && in tracePredStateThroughBlocksAndHarden()
1599 } else if (BaseMO.getReg() == X86::RIP || in hardenLoadAddr()
1611 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base") in hardenLoadAddr()
2133 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
2175 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
/external/strace/linux/x86_64/
Darch_regs.h21 #define RIP 16 macro
Duserent.h17 XLAT(8*RIP),
/external/llvm/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
Dipra-reg-usage.ll6 ; CHECK: foo Clobbered Registers: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 B…
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h55 #define RIP 128 macro
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DRegionPrinter.cpp146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
147 return &RIP->getRegionInfo(); in getGraph()
/external/llvm/lib/Analysis/
DRegionPrinter.cpp146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
147 return &RIP->getRegionInfo(); in getGraph()
/external/llvm-project/llvm/lib/Analysis/
DRegionPrinter.cpp146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
147 return &RIP->getRegionInfo(); in getGraph()
/external/llvm-project/lld/test/MachO/
Dsubsections-section-relocs.s14 ## have RIP = ADDR + 7
/external/rust/crates/libc/src/fuchsia/
Dx86_64.rs137 pub const RIP: ::c_int = 16; constant
/external/llvm-project/polly/lib/Support/
DScopHelper.cpp217 RegionInfoPass *RIP = P->getAnalysisIfAvailable<RegionInfoPass>(); in splitEntryBlockForAlloca() local
218 RegionInfo *RI = RIP ? &RIP->getRegionInfo() : nullptr; in splitEntryBlockForAlloca()
/external/google-breakpad/src/common/linux/
Dbreakpad_getcontext_unittest.cc141 CHECK_REG(RIP); in TEST()
/external/llvm/lib/Transforms/ObjCARC/
DObjCARCOpts.cpp1606 for (Instruction *RIP : NewRetainReleaseRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1607 if (ReleasesToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1610 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
1663 for (Instruction *RIP : NewReleaseRetainRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1664 if (RetainsToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1667 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()

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