| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/ |
| D | Scheduler.cpp | 41 ResourceStateEvent RSE = in isAvailable() local
43 HadTokenStall = RSE != RS_BUFFER_AVAILABLE; in isAvailable()
45 switch (RSE) { in isAvailable()
|
| /external/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| D | Scheduler.cpp | 41 ResourceStateEvent RSE = in isAvailable() local
43 HadTokenStall = RSE != RS_BUFFER_AVAILABLE; in isAvailable()
45 switch (RSE) { in isAvailable()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 261 RSE = MRI.use_end(); RSUse != RSE; ++RSUse) { in foldOperand() local
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1042 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); in hasVariant() local
1043 RSI != RSE; ++RSI) { in hasVariant()
1279 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1280 RSI != RSE; ++RSI) { in substituteVariants()
1308 RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); in inferFromTransitions() local
1309 RSI != RSE; ++RSI) { in inferFromTransitions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 589 RSUse = MRI->use_begin(RegSeqDstReg), RSE = MRI->use_end(); in foldOperand() local
590 RSUse != RSE; RSUse = Next) { in foldOperand()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 607 RSUse = MRI->use_nodbg_begin(RegSeqDstReg), RSE = MRI->use_nodbg_end(); in foldOperand() local
608 RSUse != RSE; RSUse = Next) { in foldOperand()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1637 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1638 RSI != RSE; ++RSI) { in substituteVariants()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 1657 // RSE is like RSY except with a 12 bit displacement (instead of 20).
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 1657 // RSE is like RSY except with a 12 bit displacement (instead of 20).
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart2.csv | 4162 ,"GB","RSE","Riseley","Riseley","WBK","--3-----","RL","0901",,"5121N 00056W",
10844 ,"IT","RSE","Bagno Roselle","Bagno Roselle",,"--3-----","RL","0607",,"4248N 01108E",
22833 ,"NO","RSE","Rosendal","Rosendal","12","--3-----","RL","0901",,"5959N 00601E",
|
| D | 2013-1_UNLOCODE_CodeListPart1.csv | 1980 ,"AU","RSE","Au-Rose Bay","Au-Rose Bay","NSW","---4----","AI","9912",,,
5163 ,"BE","RSE","Ressegem","Ressegem","VOV","--3-----","RN","0307",,"5053N 00354E",
7659 ,"BR","RSE","Reserva","Reserva","PR","--3-----","RQ","0607",,,
10274 ,"CA","RSE","Rosemont","Rosemont","AB","--3-----","RL","1207",,"5104N 11405W",
23246 ,"DE","RSE","Rieste","Rieste","NI","--3-----","RQ","0407",,,
33649 ,"FR","RSE","Bressuire","Bressuire","79","-23-----","RL","9805",,,
|
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 22988 ,"US","RSE","Reseda","Reseda","CA","--3-----","RQ","9307",,,
|
| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_011.ppm | 649 ���������YSSgaag_^ia`]RSE;<;01#���sklogh�����ѵ��i_`. !, >-05#': '>%,? &>%6 6 < #z[a����qvC…
|