| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ExecutionEngine/Orc/ |
| D | OrcRemoteTargetServer.h | 352 Expected<std::vector<uint8_t>> handleReadMem(JITTargetAddress RSrc, in handleReadMem() argument
354 uint8_t *Src = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(RSrc)); in handleReadMem()
357 << format("0x%016x", RSrc) << "\n"); in handleReadMem()
|
| /external/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/ |
| D | OrcRemoteTargetServer.h | 366 Expected<std::vector<uint8_t>> handleReadMem(JITTargetAddress RSrc, in handleReadMem() argument
368 uint8_t *Src = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(RSrc)); in handleReadMem()
371 << format("0x%016x", RSrc) << "\n"); in handleReadMem()
|
| /external/llvm/include/llvm/ExecutionEngine/Orc/ |
| D | OrcRemoteTargetServer.h | 365 Expected<std::vector<char>> handleReadMem(TargetAddress RSrc, uint64_t Size) { in handleReadMem() argument
366 char *Src = reinterpret_cast<char *>(static_cast<uintptr_t>(RSrc)); in handleReadMem()
369 << format("0x%016x", RSrc) << "\n"); in handleReadMem()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1379 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
1418 MIB.addUse(RSrc) in selectStoreIntrinsic()
2959 Register RSrc = MI.getOperand(2).getReg(); // SGPR in getInstrMapping() local
2963 unsigned Size2 = MRI.getType(RSrc).getSizeInBits(); in getInstrMapping()
2966 unsigned RSrcBank = getRegBankID(RSrc, MRI, *TRI); in getInstrMapping()
3141 Register RSrc = MI.getOperand(2).getReg(); // SGPR in getInstrMapping() local
3146 unsigned Size2 = MRI.getType(RSrc).getSizeInBits(); in getInstrMapping()
3150 unsigned RSrcBank = getRegBankID(RSrc, MRI, *TRI); in getInstrMapping()
|
| D | AMDGPUInstructionSelector.cpp | 986 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
1010 MIB.addUse(RSrc) in selectStoreIntrinsic()
|
| D | AMDGPUISelDAGToDAG.cpp | 220 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
|
| D | SIInstrInfo.cpp | 334 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandWithOffset() local
337 if (RSrc->getReg() != MFI->getScratchRSrcReg()) in getMemOperandWithOffset()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 3619 Register RSrc = MI.getOperand(2).getReg(); in legalizeBufferStore() local
3680 .addUse(RSrc) // rsrc in legalizeBufferStore()
3708 Register RSrc = MI.getOperand(2).getReg(); in legalizeBufferLoad() local
3783 .addUse(RSrc) // rsrc in legalizeBufferLoad()
3905 Register RSrc = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferAtomic() local
3941 MIB.addUse(RSrc) // rsrc in legalizeBufferAtomic()
|
| D | AMDGPURegisterBankInfo.cpp | 1466 Register RSrc = MI.getOperand(1).getReg(); in applyMappingSBufferLoad() local
1489 .addUse(RSrc) // rsrc in applyMappingSBufferLoad()
1510 OpsToWaterfall.insert(RSrc); in applyMappingSBufferLoad()
1800 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
1839 MIB.addUse(RSrc) in selectStoreIntrinsic()
|
| D | AMDGPUInstructionSelector.cpp | 3876 Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass); in buildRSRC() local
3904 .addDef(RSrc) in buildRSRC()
3910 return RSrc; in buildRSRC()
|
| D | SIInstrInfo.cpp | 355 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandsWithOffsetWidth() local
358 if (RSrc->getReg() != MFI->getScratchRSrcReg()) in getMemOperandsWithOffsetWidth()
363 BaseOps.push_back(RSrc); in getMemOperandsWithOffsetWidth()
|
| D | AMDGPUISelDAGToDAG.cpp | 228 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 102 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
|