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/external/llvm-project/llvm/test/CodeGen/RISCV/
Dframe-info.ll3 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
7 ; RUN: | FileCheck -check-prefix=RV64-WITHFP %s
14 ; RV64-LABEL: trivial:
15 ; RV64: # %bb.0:
16 ; RV64-NEXT: ret
33 ; RV64-WITHFP-LABEL: trivial:
34 ; RV64-WITHFP: # %bb.0:
35 ; RV64-WITHFP-NEXT: addi sp, sp, -16
36 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
37 ; RV64-WITHFP-NEXT: sd ra, 8(sp)
[all …]
Dshadowcallstack.ll5 ; RUN: | FileCheck %s --check-prefix=RV64
12 ; RV64-LABEL: f1:
13 ; RV64: # %bb.0:
14 ; RV64-NEXT: ret
25 ; RV64-LABEL: f2:
26 ; RV64: # %bb.0:
27 ; RV64-NEXT: tail foo
50 ; RV64-LABEL: f3:
51 ; RV64: # %bb.0:
52 ; RV64-NEXT: sd ra, 0(s2)
[all …]
Dinterrupt-attr.ll10 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
12 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F
14 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
299 ; CHECK-RV64-LABEL: foo_with_call:
300 ; CHECK-RV64: # %bb.0:
301 ; CHECK-RV64-NEXT: addi sp, sp, -128
302 ; CHECK-RV64-NEXT: sd ra, 120(sp)
303 ; CHECK-RV64-NEXT: sd t0, 112(sp)
304 ; CHECK-RV64-NEXT: sd t1, 104(sp)
305 ; CHECK-RV64-NEXT: sd t2, 96(sp)
[all …]
Dtls-models.ll5 ; RUN: | FileCheck -check-prefix=RV64-PIC %s
7 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64-NOPIC %s
35 ; RV64-PIC-LABEL: f1:
36 ; RV64-PIC: # %bb.0: # %entry
37 ; RV64-PIC-NEXT: addi sp, sp, -16
38 ; RV64-PIC-NEXT: sd ra, 8(sp)
39 ; RV64-PIC-NEXT: .LBB0_1: # %entry
40 ; RV64-PIC-NEXT: # Label of block must be emitted
41 ; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified)
42 ; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
[all …]
Dfastcc-int.ll5 ; RUN: | FileCheck -check-prefix=RV64 %s
12 ; RV64-LABEL: callee:
13 ; RV64: # %bb.0:
14 ; RV64-NEXT: ret
53 ; RV64-LABEL: caller:
54 ; RV64: # %bb.0:
55 ; RV64-NEXT: addi sp, sp, -48
56 ; RV64-NEXT: sd ra, 40(sp)
57 ; RV64-NEXT: sd s0, 32(sp)
58 ; RV64-NEXT: ld t0, 0(a0)
[all …]
Dlegalize-fneg.ll5 ; RUN: | FileCheck -check-prefix=RV64 %s
16 ; RV64-LABEL: test1:
17 ; RV64: # %bb.0: # %entry
18 ; RV64-NEXT: lw a1, 0(a1)
19 ; RV64-NEXT: addi a2, zero, 1
20 ; RV64-NEXT: slli a2, a2, 31
21 ; RV64-NEXT: xor a1, a1, a2
22 ; RV64-NEXT: sw a1, 0(a0)
23 ; RV64-NEXT: ret
42 ; RV64-LABEL: test2:
[all …]
Dpic-models.ll7 ; RUN: | FileCheck -check-prefix=RV64-STATIC %s
9 ; RUN: | FileCheck -check-prefix=RV64-PIC %s
35 ; RV64-STATIC-LABEL: f1:
36 ; RV64-STATIC: # %bb.0: # %entry
37 ; RV64-STATIC-NEXT: lui a0, %hi(external_var)
38 ; RV64-STATIC-NEXT: addi a0, a0, %lo(external_var)
39 ; RV64-STATIC-NEXT: ret
41 ; RV64-PIC-LABEL: f1:
42 ; RV64-PIC: # %bb.0: # %entry
43 ; RV64-PIC-NEXT: .LBB0_1: # %entry
[all …]
Dneg-abs.ll3 … llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown | FileCheck %s --check-prefix=RV64
16 ; RV64-LABEL: neg_abs32:
17 ; RV64: # %bb.0:
18 ; RV64-NEXT: sraiw a1, a0, 31
19 ; RV64-NEXT: xor a0, a0, a1
20 ; RV64-NEXT: subw a0, a1, a0
21 ; RV64-NEXT: ret
35 ; RV64-LABEL: select_neg_abs32:
36 ; RV64: # %bb.0:
37 ; RV64-NEXT: sraiw a1, a0, 31
[all …]
Dcmp-bool.ll3 ; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64 %s
14 ; RV64-LABEL: bool_eq:
15 ; RV64: # %bb.0: # %entry
16 ; RV64-NEXT: beq a0, a1, .LBB0_2
17 ; RV64-NEXT: # %bb.1: # %if.end
18 ; RV64-NEXT: ret
19 ; RV64-NEXT: .LBB0_2: # %if.then
20 ; RV64-NEXT: jr a2
42 ; RV64-LABEL: bool_ne:
43 ; RV64: # %bb.0: # %entry
[all …]
Dsdata-limit-8.ll2 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
14 ; RV64: .section .sbss
15 ; RV64: .section .sdata
Dsdata-limit-0.ll2 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
13 ; RV64-NOT: .section .sbss
14 ; RV64-NOT: .section .sdata
Dsdata-limit-4.ll2 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
14 ; RV64: .section .sbss
15 ; RV64-NOT: .section .sdata
Dsdata-local-sym.ll2 ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s
15 ; RV64: .section .sbss
16 ; RV64: .section .sdata
Dmattr-invalid-combination.ll4 ; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
/external/llvm-project/lld/test/ELF/
Demulation-riscv.s40 # RUN: llvm-readobj --file-headers %t | FileCheck --check-prefix=RV64 %s
42 # RUN: llvm-readobj --file-headers %t | FileCheck --check-prefix=RV64 %s
45 # RUN: llvm-readobj --file-headers %t | FileCheck --check-prefix=RV64 %s
47 # RV64: ElfHeader {
48 # RV64-NEXT: Ident {
49 # RV64-NEXT: Magic: (7F 45 4C 46)
50 # RV64-NEXT: Class: 64-bit (0x2)
51 # RV64-NEXT: DataEncoding: LittleEndian (0x1)
52 # RV64-NEXT: FileVersion: 1
53 # RV64-NEXT: OS/ABI: SystemV (0x0)
[all …]
/external/llvm-project/llvm/test/MC/RISCV/
Delf-header.s4 # RUN: | FileCheck -check-prefix=RV64 %s
25 # RV64: Format: elf64-littleriscv
26 # RV64: Arch: riscv64
27 # RV64: AddressSize: 64bit
28 # RV64: ElfHeader {
29 # RV64: Ident {
30 # RV64: Magic: (7F 45 4C 46)
31 # RV64: Class: 64-bit (0x2)
32 # RV64: DataEncoding: LittleEndian (0x1)
33 # RV64: FileVersion: 1
[all …]
Drv64c-valid.s13 # RUN: | FileCheck -check-prefixes=CHECK-NO-RV64 %s
20 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
25 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
30 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
35 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
44 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
50 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
55 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
61 # CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
Drvi-pseudos.s4 # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-NOPIC,CHECK-RV64
8 # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-PIC,CHECK-RV64,CHECK-PIC-RV64
46 # CHECK-PIC-RV64: ld a0, %pcrel_lo(.Lpcrel_hi6)(a0)
54 # CHECK-PIC-RV64: ld a1, %pcrel_lo(.Lpcrel_hi7)(a1)
63 # CHECK-PIC-RV64: ld a2, %pcrel_lo(.Lpcrel_hi8)(a2)
71 # CHECK-PIC-RV64: ld a3, %pcrel_lo(.Lpcrel_hi9)(a3)
79 # CHECK-PIC-RV64: ld a4, %pcrel_lo(.Lpcrel_hi10)(a4)
85 # CHECK-RV64: ld a0, %pcrel_lo(.Lpcrel_hi11)(a0)
91 # CHECK-RV64: ld a1, %pcrel_lo(.Lpcrel_hi12)(a1)
98 # CHECK-RV64: ld a2, %pcrel_lo(.Lpcrel_hi13)(a2)
[all …]
Dinvalid-instruction-spellcheck.s4 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64I %s
8 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64IF %s
15 # CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, sd
27 # CHECK-RV64: did you mean: add, addi, addw
Drvc-hints-invalid.s4 # RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64 %s
21 c.slli x0, 0 # CHECK-RV64: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
/external/llvm-project/llvm/test/DebugInfo/RISCV/
Deh-frame.s4 # RUN: | FileCheck --check-prefixes=CHECK,RV64 %s
16 # TODO: gas uses -4 for the data alignment factor for both RV32 and RV64. They
21 # RV64: Data alignment factor: -8
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td86 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
100 [RV32, RV64, DefaultMode],
106 [RV32, RV64, DefaultMode],
121 [RV32, RV64, DefaultMode],
134 [RV32, RV64, DefaultMode],
143 [RV32, RV64, DefaultMode],
156 [RV32, RV64, DefaultMode],
162 [RV32, RV64, DefaultMode],
DRISCV.td59 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
67 def RV64 : HwMode<"+64bit">;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td109 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
123 [RV32, RV64],
129 [RV32, RV64],
144 [RV32, RV64],
157 [RV32, RV64],
166 [RV32, RV64],
179 [RV32, RV64],
185 [RV32, RV64],
/external/llvm-project/llvm/lib/Support/
DTargetParser.cpp275 #define PROC_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32)) in resolveTuneCPUAlias() argument
306 #define PROC_ALIAS(NAME, RV32, RV64) Values.emplace_back(StringRef(NAME)); in fillValidTuneCPUArchList() argument

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