Searched refs:R_BIT (Results 1 – 9 of 9) sorted by relevance
1050 ((texGenEnabled & R_BIT) && planeR[0] != 0.0) || in r200_need_dis_texgen()1057 ((texGenEnabled & R_BIT) && planeR[1] != 0.0) || in r200_need_dis_texgen()1062 if (!(texGenEnabled & R_BIT)) { in r200_need_dis_texgen()1066 needtgenable |= R_BIT; in r200_need_dis_texgen()1072 ((texGenEnabled & R_BIT) && planeR[3] != 0.0)) { in r200_need_dis_texgen()1128 if (texUnit->TexGenEnabled & R_BIT) { in r200_validate_texgen()1174 if (needtgenable & (R_BIT)) { in r200_validate_texgen()1185 (texUnit->TexGenEnabled & R_BIT) ? texUnit->GenR.ObjectPlane : I + 8, in r200_validate_texgen()1202 if (needtgenable & (R_BIT)) { in r200_validate_texgen()1212 (texUnit->TexGenEnabled & R_BIT) ? texUnit->GenR.EyePlane : I + 8, in r200_validate_texgen()[all …]
433 if (texUnit->TexGenEnabled & R_BIT) { in texgen()526 else if (texUnit->TexGenEnabled & R_BIT) in validate_texgen_stage()537 if (texUnit->TexGenEnabled == (S_BIT|T_BIT|R_BIT)) { in validate_texgen_stage()
811 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) { in radeon_validate_texgen()827 if ( ((texUnit->TexGenEnabled & R_BIT) && in radeon_validate_texgen()846 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) { in radeon_validate_texgen()
268 if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) in radeonEmitArrays()
354 if ( (ctx->Texture.FixedFuncUnit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) in radeonEmitArrays()
350 if (texUnit->TexGenEnabled & R_BIT) { in compute_texgen()
628 if (texUnit->TexGenEnabled & R_BIT) { in update_texgen()
787 _mesa_set_enable(ctx, GL_TEXTURE_GEN_R, !!(genEnabled & R_BIT)); in pop_enable_group()851 _mesa_set_enable(ctx, GL_TEXTURE_GEN_R, !!(unit->TexGenEnabled & R_BIT)); in pop_texture_group()
1138 #define R_BIT 4 macro1140 #define STR_BITS (S_BIT | T_BIT | R_BIT)