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Searched refs:RawbitsToFloat (Results 1 – 15 of 15) sorted by relevance

/external/vixl/src/
Dutils-vixl.cc35 const float kFP32DefaultNaN = RawbitsToFloat(0x7fc00000);
45 const float kFP32PositiveInfinity = RawbitsToFloat(0x7f800000);
46 const float kFP32NegativeInfinity = RawbitsToFloat(0xff800000);
81 float RawbitsToFloat(uint32_t bits) { in RawbitsToFloat() function
158 return RawbitsToFloat(bits); in FloatPack()
330 return RawbitsToFloat((sign << 31) | (exponent << kFloatMantissaBits) | in FPToFloat()
364 return RawbitsToFloat((sign << 31) | (exponent << 23) | payload); in FPToFloat()
Dutils-vixl.h273 float RawbitsToFloat(uint32_t bits);
276 return RawbitsToFloat(bits); in rawbits_to_float()
455 return RawbitsToFloat(FloatToRawbits(num) | kFP32QuietNaNMask); in ToQuietNaN()
701 return RawbitsToFloat(result); in Imm8ToFP32()
1320 return RawbitsToFloat(bits); in FPRoundToFloat()
1390 return StaticCastFPTo<T>(RawbitsToFloat(static_cast<uint32_t>(value))); in RawbitsWithSizeToFP()
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc424 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s6); in TEST()
1006 float s1 = RawbitsToFloat(0x7f951111); in TEST()
1007 float s2 = RawbitsToFloat(0x7f952222); in TEST()
1008 float sa = RawbitsToFloat(0x7f95aaaa); in TEST()
1009 float q1 = RawbitsToFloat(0x7fea1111); in TEST()
1010 float q2 = RawbitsToFloat(0x7fea2222); in TEST()
1011 float qa = RawbitsToFloat(0x7feaaaaa); in TEST()
1020 float s1_proc = RawbitsToFloat(0x7fd51111); in TEST()
1021 float s2_proc = RawbitsToFloat(0x7fd52222); in TEST()
1022 float sa_proc = RawbitsToFloat(0x7fd5aaaa); in TEST()
[all …]
Dtest-utils-aarch64.cc47 const float kFP32SignallingNaN = RawbitsToFloat(0x7f807c01);
52 const float kFP32QuietNaN = RawbitsToFloat(0x7fc07e01);
Dtest-utils-aarch64.h149 return RawbitsToFloat(sreg_bits(code)); in sreg()
Dtest-assembler-sve-aarch64.cc17429 float sa = RawbitsToFloat(0x7f951111); in TEST_SVE()
17430 float sn = RawbitsToFloat(0x7f952222); in TEST_SVE()
17431 float sm = RawbitsToFloat(0x7f953333); in TEST_SVE()
17432 float qa = RawbitsToFloat(0x7fea1111); in TEST_SVE()
17433 float qn = RawbitsToFloat(0x7fea2222); in TEST_SVE()
17434 float qm = RawbitsToFloat(0x7fea3333); in TEST_SVE()
17999 float fp32_sn = RawbitsToFloat(0x7f952222); in TEST_SVE()
18000 float fp32_qn = RawbitsToFloat(0x7fea2222); in TEST_SVE()
Dtest-simulator-aarch64.cc165 static float rawbits_to_fp(uint32_t bits) { return RawbitsToFloat(bits); } in rawbits_to_fp()
Dtest-assembler-aarch64.cc7836 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) & kSRegMask), s16); in TEST()
7837 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) >> kSRegSize), s17); in TEST()
/external/vixl/test/aarch32/
Dtest-utils-aarch32.cc226 RawbitsToFloat(result), in EqualFP32()
Dtest-assembler-aarch32.cc4078 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s3); in TEST_T32()
4171 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s3); in TEST_T32()
4235 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s4); in TEST_T32()
4244 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s3); in TEST_T32()
4307 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s4); in TEST_T32()
4316 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s3); in TEST_T32()
4392 ASSERT_EQUAL_FP32(RawbitsToFloat(0x89abcdef), s3); in TEST_T32()
Dtest-disasm-a32.cc2426 COMPARE_BOTH(Vmov(s2, RawbitsToFloat(0x0000db6c)), in TEST()
2429 COMPARE_BOTH(Vmov(s3, RawbitsToFloat(0x327b23c6)), in TEST()
2433 COMPARE_BOTH(Vmov(s4, RawbitsToFloat(0xffcc7fff)), in TEST()
2436 COMPARE_BOTH(Vmov(s5, RawbitsToFloat(0xb72df575)), in TEST()
/external/vixl/src/aarch64/
Dinstructions-aarch64.h631 float GetLiteralFP32() const { return RawbitsToFloat(GetLiteral32()); } in GetLiteralFP32()
Dinstructions-aarch64.cc797 return RawbitsToFloat(result); in Imm8ToFP32()
Dmacro-assembler-sve-aarch64.cc395 fp_imm = RawbitsToFloat(imm.AsUint32()); in Cpy()
Dsimulator-aarch64.cc151 VIXL_ASSERT(IsSignallingNaN(RawbitsToFloat(nan_bits & kSRegMask))); in ResetVRegisters()