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Searched refs:RdHi (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/llvm/test/MC/ARM/
Dequal-rdhi-rdlo-diagnostics.s5 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
7 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
9 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
11 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
13 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
15 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
17 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
19 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
21 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
23 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc127 // Operand: RdHi
160 // Operand: RdHi
227 // Operand: RdHi
260 // Operand: RdHi
DARMGenMCCodeEmitter.inc6807 // op: RdHi
15187 // op: RdHi
15639 // op: RdHi
15682 // op: RdHi
15905 // op: RdHi
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td3837 bits<4> RdHi;
3840 let Inst{19-16} = RdHi;
3849 bits<4> RdHi;
3852 let Inst{19-16} = RdHi;
3914 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3916 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3919 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3921 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3924 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3925 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
[all …]
DARMInstrThumb2.td543 bits<4> RdHi;
551 let Inst{11-8} = RdHi;
560 bits<4> RdHi;
568 let Inst{11-8} = RdHi;
2573 (outs rGPR:$RdLo, rGPR:$RdHi),
2575 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2578 (outs rGPR:$RdLo, rGPR:$RdHi),
2580 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2585 (outs rGPR:$RdLo, rGPR:$RdHi),
2587 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
[all …]
DARMInstrFormats.td888 bits<4> RdHi;
889 let Inst{19-16} = RdHi;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td4230 bits<4> RdHi;
4233 let Inst{19-16} = RdHi;
4242 bits<4> RdHi;
4245 let Inst{19-16} = RdHi;
4312 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4314 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4315 [(set GPR:$RdLo, GPR:$RdHi,
4320 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4322 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4323 [(set GPR:$RdLo, GPR:$RdHi,
[all …]
DARMInstrThumb2.td681 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
682 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
685 bits<4> RdHi;
693 let Inst{11-8} = RdHi;
698 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
700 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
701 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
704 bits<4> RdHi;
712 let Inst{11-8} = RdHi;
2959 [(set rGPR:$RdLo, rGPR:$RdHi,
[all …]
DARMInstrFormats.td1012 bits<4> RdHi;
1013 let Inst{19-16} = RdHi;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td4080 bits<4> RdHi;
4083 let Inst{19-16} = RdHi;
4092 bits<4> RdHi;
4095 let Inst{19-16} = RdHi;
4162 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4164 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4165 [(set GPR:$RdLo, GPR:$RdHi,
4170 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4172 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4173 [(set GPR:$RdLo, GPR:$RdHi,
[all …]
DARMInstrThumb2.td680 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
681 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
684 bits<4> RdHi;
692 let Inst{11-8} = RdHi;
697 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
699 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
700 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
703 bits<4> RdHi;
711 let Inst{11-8} = RdHi;
2890 [(set rGPR:$RdLo, rGPR:$RdHi,
[all …]
DARMInstrFormats.td1006 bits<4> RdHi;
1007 let Inst{19-16} = RdHi;
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td399 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $status",
401 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$status),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td431 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
433 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch),
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td431 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
433 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch),
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp2306 IValueT RdHi = encodeGPRegister(OpRdHi, "RdHi", UmullName); in umull() local
2310 verifyRegNotPc(RdHi, "RdHi", UmullName); in umull()
2313 verifyRegsNotEq(RdHi, "RdHi", RdLo, "RdLo", UmullName); in umull()
2316 emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags); in umull()
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc9054 // (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9069 // (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9265 // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9280 // (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
/external/llvm-project/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp8151 unsigned RdHi = Inst.getOperand(0).getReg(); in validateInstruction() local
8153 if(RdHi == RdLo) { in validateInstruction()