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Searched refs:Rdm (Results 1 – 12 of 12) sorted by relevance

/external/vixl/test/aarch32/config/
Dcond-rd-operand-rn-shift-rs-t32.json28 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs>
29 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
30 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs>
31 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs>
36 "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
37 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
38 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
39 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
41 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
[all …]
Dcond-rd-rn-operand-rm-t32.json33 // MNEMONIC{<c>}.N <Rdm>, SP, <Rdm>
54 // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
122 "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
125 "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
128 "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
131 "Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
134 "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
137 "Lsrs", // LSRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
140 "Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
143 "Rors" // RORS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
[all …]
Dcond-rdlow-rnlow-rmlow-t32.json28 // MNEMONIC{<c>}.N <Rdm>, <Rn>, <Rdm>
32 "Mul", // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
33 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
77 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
93 "Mul" // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td1138 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1561 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1562 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1563 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1564 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1565 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1566 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td1233 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1740 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1741 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1742 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1743 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1744 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1745 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td1245 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1752 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1753 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1754 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1755 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1756 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1757 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
/external/capstone/arch/ARM/
DARMDisassembler.c3886 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); in DecodeThumbAddSPReg() local
3887 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3889 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3892 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
DARMGenAsmWriter.inc11737 // (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)
11810 // (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)
11821 // (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)
11859 // (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, pred:$p)
/external/rust/crates/nix/src/sys/socket/
Dmod.rs75 Rdm = libc::SOCK_RDM, enumerator
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg() local
3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
/external/llvm-project/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp4410 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg() local
4411 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
4413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
4416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp4389 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg() local
4390 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
4392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
4395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()