| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 30 typedef std::vector<Record*> RecVec; typedef
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
186 RecVec ItinDefList;
190 RecVec ItinRWDefs;
194 RecVec UnsupportedFeaturesDefs;
197 RecVec WriteResDefs;
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| D | CodeGenSchedule.cpp | 139 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); in collectProcModels()
179 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, in scanSchedRW()
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
212 RecVec SWDefs, SRDefs; in collectSchedRW()
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
228 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedRW()
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
243 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectSchedRW()
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| D | SubtargetEmitter.cpp | 97 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
617 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
753 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
760 RecVec SubResources; in ExpandProcResources()
783 RecVec SuperResources = PR->getValueAsListOfDefs("Resources"); in ExpandProcResources()
875 RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses"); in GenSchedClassTables()
927 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()
971 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
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| D | RegisterInfoEmitter.cpp | 1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
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| D | CodeGenRegisters.cpp | 676 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 241 const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl"); in checkSTIPredicates()
255 const RecVec Defs = in checkSTIPredicates()
258 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes"); in checkSTIPredicates()
299 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
305 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
330 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
337 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
404 RecVec RV = Records.getAllDerivedDefinitions("STIPredicate"); in collectSTIPredicates()
440 RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in checkMCInstPredicates()
462 RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit"); in collectRetireControlUnits()
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| D | CodeGenSchedule.h | 33 using RecVec = std::vector<Record*>; variable
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
229 RecVec ItinDefList;
233 RecVec ItinRWDefs;
237 RecVec UnsupportedFeaturesDefs;
240 RecVec WriteResDefs;
241 RecVec ReadAdvanceDefs;
244 RecVec ProcResourceDefs;
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| D | PredicateExpander.h | 55 using RecVec = std::vector<Record *>; variable
72 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
73 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
74 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
89 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
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| D | PredicateExpander.cpp | 118 const RecVec &Opcodes) { in expandCheckOpcode()
148 const RecVec &Opcodes) { in expandCheckPseudo()
156 const RecVec &Sequence, in expandPredicateSequence()
242 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
256 const RecVec &Cases, in expandOpcodeSwitchStatement()
424 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
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| D | SubtargetEmitter.cpp | 111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
179 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask()
234 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
268 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
269 RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures"); in CPUKeyValues()
301 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
314 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
361 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
392 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
406 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
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| D | DFAPacketizerEmitter.cpp | 84 void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
193 const RecVec &Itineraries) { in createScheduleClasses()
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| D | InstrInfoEmitter.cpp | 438 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
487 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
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| D | RegisterInfoEmitter.cpp | 1551 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
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| D | CodeGenRegisters.cpp | 758 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
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| /external/llvm/include/llvm/TableGen/ |
| D | SetTheory.h | 65 typedef std::vector<Record*> RecVec; typedef
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
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| /external/llvm-project/llvm/include/llvm/TableGen/ |
| D | SetTheory.h | 66 using RecVec = std::vector<Record *>;
97 using ExpandMap = std::map<Record *, RecVec>;
139 const RecVec *expand(Record *Set);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/TableGen/ |
| D | SetTheory.h | 66 using RecVec = std::vector<Record *>;
97 using ExpandMap = std::map<Record *, RecVec>;
139 const RecVec *expand(Record *Set);
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| /external/llvm/lib/TableGen/ |
| D | SetTheory.cpp | 26 typedef SetTheory::RecVec RecVec; typedef
220 if (const RecVec *Result = ST.expand(Rec)) in apply()
275 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
298 const RecVec *SetTheory::expand(Record *Set) { in expand()
313 RecVec &EltVec = Expansions[Set]; in expand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/TableGen/ |
| D | SetTheory.cpp | 36 using RecVec = SetTheory::RecVec; typedef
230 if (const RecVec *Result = ST.expand(Rec)) in apply()
285 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
308 const RecVec *SetTheory::expand(Record *Set) { in expand()
323 RecVec &EltVec = Expansions[Set]; in expand()
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| /external/llvm-project/llvm/lib/TableGen/ |
| D | SetTheory.cpp | 36 using RecVec = SetTheory::RecVec; typedef
230 if (const RecVec *Result = ST.expand(Rec)) in apply()
285 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
308 const RecVec *SetTheory::expand(Record *Set) { in expand()
323 RecVec &EltVec = Expansions[Set]; in expand()
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