| /external/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 16 glm_uvec4 Reg1; in glm_i128_interleave() local
22 Reg1 = x; in glm_i128_interleave()
26 Reg2 = _mm_slli_si128(Reg1, 2); in glm_i128_interleave()
27 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
28 Reg1 = _mm_and_si128(Reg1, Mask4); in glm_i128_interleave()
32 Reg2 = _mm_slli_si128(Reg1, 1); in glm_i128_interleave()
33 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
34 Reg1 = _mm_and_si128(Reg1, Mask3); in glm_i128_interleave()
38 Reg2 = _mm_slli_epi32(Reg1, 4); in glm_i128_interleave()
39 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
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| /external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
| D | TargetTest.cpp | 91 const unsigned Reg1 = Mips::T1; in TEST_F() local
92 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), in TEST_F()
93 ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true), in TEST_F()
94 IsLoadLow16BitImm(Reg1, 0xFFFFU, true))); in TEST_F()
103 const unsigned Reg1 = Mips::T1_64; in TEST_F() local
104 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), in TEST_F()
105 ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false), in TEST_F()
106 IsLoadLow16BitImm(Reg1, 0xFFFFU, false))); in TEST_F()
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
464 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
483 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
650 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
669 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
650 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
669 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
95 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
98 GPRRegister::Encoded_Reg_##Reg1); \ in TEST_F()
101 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
107 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
120 GPRRegister::Encoded_Reg_##Reg1 < 4) { \ in TEST_F()
[all …]
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| /external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/ |
| D | llvm-prefer-register-over-unsigned.cpp | 24 unsigned Reg1 = getReg(); in apply_1() local
52 llvm::Register Reg1 = getReg(); in done_1() local
74 unsigned Reg1 = getRegLike(); in do_nothing_1() local
|
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
97 __ mov(IceType_i##Size, Encoded_GPR_##Reg1(), Immediate(Value1)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
100 __ And(IceType_i32, Encoded_GPR_##Reg1(), Immediate(Mask##Size)); \ in TEST_F()
105 ASSERT_EQ(V0, test.Reg1()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
875 unsigned Reg1; member
905 RPI.Reg1 = CSI[i].getReg(); in computeCalleeSaveRegisterPairs()
907 assert(AArch64::GPR64RegClass.contains(RPI.Reg1) || in computeCalleeSaveRegisterPairs()
908 AArch64::FPR64RegClass.contains(RPI.Reg1)); in computeCalleeSaveRegisterPairs()
909 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
992 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); in spillCalleeSavedRegisters()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
509 .addImm(Reg1) in InsertSEH()
519 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
520 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
527 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
557 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
560 .addImm(Reg1) in InsertSEH()
568 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
569 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
576 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
[all …]
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
614 uint16_t Reg1; variable
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
636 Reg0 = Reg1;
637 Reg1 = 0;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 696 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
699 .addImm(Reg1) in InsertSEH()
709 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
710 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
717 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
747 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
750 .addImm(Reg1) in InsertSEH()
758 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
759 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
766 .addImm(RegInfo->getSEHRegNum(Reg1)) in InsertSEH()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 419 bool parseAddress(bool &HaveReg1, Register &Reg1,
835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
853 if (parseRegister(Reg1)) in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
911 if (parseAddressRegister(Reg1)) in parseAddress()
913 Base = Regs[Reg1.Num]; in parseAddress()
928 if (parseAddressRegister(Reg1)) in parseAddress()
933 Index = Regs[Reg1.Num]; in parseAddress()
935 Base = Regs[Reg1.Num]; in parseAddress()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
|
| D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 128 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
130 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
132 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
134 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
138 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
|
| D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| /external/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 415 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
947 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
986 if (parseRegister(Reg1)) in parseAddress()
1005 if (parseIntegerRegister(Reg1, RegGroup)) in parseAddress()
1059 Register Reg1, Reg2; in parseAddress() local
1066 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, in parseAddress()
1081 if (parseAddressRegister(Reg1)) in parseAddress()
1083 Base = Regs[Reg1.Num]; in parseAddress()
1094 if (parseAddressRegister(Reg1)) in parseAddress()
1099 Index = Regs[Reg1.Num]; in parseAddress()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
778 unsigned Temp = Reg1; in EmitInstrRegReg()
779 Reg1 = Reg2; in EmitInstrRegReg()
783 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
793 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
804 unsigned temp = Reg1; in EmitMovFPIntPair()
805 Reg1 = Reg2; in EmitMovFPIntPair()
808 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
78 return contains(Reg1) && contains(Reg2); in contains()
740 uint16_t Reg1 = 0; variable
748 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
764 Reg0 = Reg1;
765 Reg1 = 0;
|
| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
78 return contains(Reg1) && contains(Reg2); in contains()
741 uint16_t Reg1 = 0; variable
749 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
765 Reg0 = Reg1;
766 Reg1 = 0;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 187 unsigned Reg1,
402 unsigned Reg1, in getOperandGatherWeight() argument
415 if (Def->modifiesRegister(Reg1, TRI)) in getOperandGatherWeight()
540 unsigned Reg1 = OperandMasks[I].Reg; in collectCandidates() local
549 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) << in collectCandidates()
552 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles); in collectCandidates()
557 unsigned FreeBanks1 = getFreeBanks(Reg1, SubReg1, Mask1, UsedBanks); in collectCandidates()
560 Candidates.push(Candidate(&MI, Reg1, FreeBanks1, Weight in collectCandidates()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
214 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
220 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
226 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
232 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
239 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
242 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
211 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
229 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
239 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
[all …]
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