| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | PBQPRAConstraint.h | 25 namespace RegAlloc {
33 using PBQPRAGraph = PBQP::RegAlloc::PBQPRAGraph;
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| D | RegAllocPBQP.h | 45 namespace RegAlloc {
171 using AllowedRegVector = RegAlloc::AllowedRegVector;
283 using NodeMetadata = RegAlloc::NodeMetadata;
285 using GraphMetadata = RegAlloc::GraphMetadata;
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | PBQPRAConstraint.h | 25 namespace RegAlloc {
33 using PBQPRAGraph = PBQP::RegAlloc::PBQPRAGraph;
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| D | RegAllocPBQP.h | 43 namespace RegAlloc {
169 using AllowedRegVector = RegAlloc::AllowedRegVector;
281 using NodeMetadata = RegAlloc::NodeMetadata;
283 using GraphMetadata = RegAlloc::GraphMetadata;
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| /external/llvm/include/llvm/CodeGen/ |
| D | PBQPRAConstraint.h | 24 namespace RegAlloc {
35 typedef PBQP::RegAlloc::PBQPRAGraph PBQPRAGraph;
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| D | RegAllocPBQP.h | 31 namespace RegAlloc {
182 typedef RegAlloc::AllowedRegVector AllowedRegVector;
342 typedef RegAlloc::NodeMetadata NodeMetadata;
344 typedef RegAlloc::GraphMetadata GraphMetadata;
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_ra.cpp | 224 class RegAlloc class
227 RegAlloc(Program *program) : prog(program), sequence(0) { } in RegAlloc() function in nv50_ir::RegAlloc
373 RegAlloc::BuildIntervalsPass::addLiveRange(Value *val, in addLiveRange()
397 RegAlloc::PhiMovesPass::needNewElseBlock(BasicBlock *b, BasicBlock *p) in needNewElseBlock()
428 RegAlloc::PhiMovesPass::splitEdges(BasicBlock *bb) in splitEdges()
502 RegAlloc::PhiMovesPass::visit(BasicBlock *bb) in visit()
532 RegAlloc::ArgumentMovesPass::visit(BasicBlock *bb) in visit()
600 RegAlloc::buildLiveSets(BasicBlock *bb) in buildLiveSets()
663 RegAlloc::BuildIntervalsPass::collectLiveValues(BasicBlock *bb) in collectLiveValues()
687 RegAlloc::BuildIntervalsPass::visit(BasicBlock *bb) in visit()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegAllocPBQP.cpp | 207 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost; in apply()
216 using AllowedRegVecPtr = const PBQP::RegAlloc::AllowedRegVector *;
738 if (AllocOpt != PBQP::RegAlloc::getSpillOptionIdx()) { in mapPBQPToRegAlloc()
865 PBQP::Solution Solution = PBQP::RegAlloc::solve(G); in runOnMachineFunction()
883 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, in PrintNodeInfo()
884 const PBQP::RegAlloc::PBQPRAGraph &G) { in PrintNodeInfo()
895 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const { in dump()
916 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const { in dump()
921 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const { in printDot()
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| D | TargetPassConfig.cpp | 901 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), variable
1113 RegisterRegAlloc::setDefault(RegAlloc); in initializeDefaultRegisterAllocatorOnce()
1154 if (RegAlloc != &useDefaultRegisterAllocator && in addRegAssignmentFast()
1155 RegAlloc != &createFastRegisterAllocator) in addRegAssignmentFast()
1184 return RegAlloc.getNumOccurrences() == 0; in usingDefaultRegAlloc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegAllocPBQP.cpp | 208 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost; in apply()
217 using AllowedRegVecPtr = const PBQP::RegAlloc::AllowedRegVector *;
724 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { in mapPBQPToRegAlloc()
858 PBQP::Solution Solution = PBQP::RegAlloc::solve(G); in runOnMachineFunction()
876 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, in PrintNodeInfo()
877 const PBQP::RegAlloc::PBQPRAGraph &G) { in PrintNodeInfo()
888 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const { in dump()
909 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const { in dump()
914 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const { in printDot()
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| D | TargetPassConfig.cpp | 851 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), variable
1055 RegisterRegAlloc::setDefault(RegAlloc); in initializeDefaultRegisterAllocatorOnce()
1096 if (RegAlloc != &useDefaultRegisterAllocator && in addRegAssignmentFast()
1097 RegAlloc != &createFastRegisterAllocator) in addRegAssignmentFast()
1125 return RegAlloc.getNumOccurrences() == 0; in usingDefaultRegAlloc()
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocPBQP.cpp | 178 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost; in apply()
188 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
684 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { in mapPBQPToRegAlloc()
811 PBQP::Solution Solution = PBQP::RegAlloc::solve(G); in runOnMachineFunction()
829 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, in PrintNodeInfo()
830 const PBQP::RegAlloc::PBQPRAGraph &G) { in PrintNodeInfo()
840 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const { in dump()
861 LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const { dump(dbgs()); } in dump()
863 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const { in printDot()
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| D | TargetPassConfig.cpp | 730 RegAlloc("regalloc", variable
738 Ctor = RegAlloc; in initializeDefaultRegisterAllocatorOnce()
739 RegisterRegAlloc::setDefault(RegAlloc); in initializeDefaultRegisterAllocatorOnce()
784 return RegAlloc.getNumOccurrences() == 0; in usingDefaultRegAlloc()
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | misched-readadvances.mir | 1 # Check that the extra operand for the full register added by RegAlloc does
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 44 // Enable Post RegAlloc Scheduler pass. [default = 0]
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 44 // Enable Post RegAlloc Scheduler pass. [default = 0]
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 45 // Enable Post RegAlloc Scheduler pass. [default = 0]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 641 LinearScan RegAlloc(Func); in postRegallocSplitting() local
642 RegAlloc.init(RAK_Global, SplitCandidates); in postRegallocSplitting()
643 RegAlloc.scan(RegMask); in postRegallocSplitting()
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| /external/clang/test/SemaCXX/ |
| D | overloaded-operator.cpp | 298 class RegAlloc { class
|
| /external/llvm-project/clang/test/SemaCXX/ |
| D | overloaded-operator.cpp | 298 class RegAlloc { class
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 91 bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass.
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 90 bit PostRAScheduler = false; // Enable Post RegAlloc Scheduler pass.
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 90 bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass.
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
|