/external/llvm/utils/TableGen/ |
D | CodeGenTarget.h | 71 mutable std::vector<Record*> RegAltNameIndices; variable 121 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); in getRegAltNameIndices() 122 return RegAltNameIndices; in getRegAltNameIndices()
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D | CodeGenTarget.cpp | 228 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); in ReadRegAltNameIndices() 229 std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord()); in ReadRegAltNameIndices()
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D | RegisterInfoEmitter.cpp | 141 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); in runEnums() local 144 if (RegAltNameIndices.size() > 1) { in runEnums() 149 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) in runEnums() 150 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums() 151 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
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/external/llvm-project/llvm/utils/TableGen/ |
D | CodeGenTarget.h | 54 mutable std::vector<Record*> RegAltNameIndices; variable 121 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); in getRegAltNameIndices() 122 return RegAltNameIndices; in getRegAltNameIndices()
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D | RegisterInfoEmitter.cpp | 154 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); in runEnums() local 157 if (RegAltNameIndices.size() > 1) { in runEnums() 162 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) in runEnums() 163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums() 164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
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D | CodeGenTarget.cpp | 391 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); in ReadRegAltNameIndices() 392 llvm::sort(RegAltNameIndices, LessRecord()); in ReadRegAltNameIndices()
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/external/llvm-project/llvm/test/TableGen/ |
D | AllowDuplicateRegisterNames.td | 25 let RegAltNameIndices = altidx;
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/external/llvm-project/llvm/lib/Target/VE/ |
D | VERegisterInfo.td | 101 let RegAltNameIndices = [AsmName] in { 162 } // RegAltNameIndices = [AsmName]
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/external/llvm-project/llvm/lib/Target/CSKY/ |
D | CSKYRegisterInfo.td | 51 let RegAltNameIndices = [ABIRegAltName] in { 98 let RegAltNameIndices = [ABIRegAltName] in {
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVRegisterInfo.td | 70 let RegAltNameIndices = [ABIRegAltName] in { 190 let RegAltNameIndices = [ABIRegAltName] in { 337 let RegAltNameIndices = [ABIRegAltName] in {
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVRegisterInfo.td | 47 let RegAltNameIndices = [ABIRegAltName] in { 167 let RegAltNameIndices = [ABIRegAltName] in {
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/external/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 89 let RegAltNameIndices = [ptr] in {
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 88 let RegAltNameIndices = [ptr] in {
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/external/capstone/contrib/sysz_update/ |
D | 0001-capstone-generate-GenRegisterInfo.inc.patch | 104 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
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/external/llvm-project/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 88 let RegAltNameIndices = [ptr] in {
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/external/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 319 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in { 354 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 355 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in { 390 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 352 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in { 387 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 92 let RegAltNameIndices = [RegNamesRaw] in {
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 92 let RegAltNameIndices = [RegNamesRaw] in {
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/external/llvm/include/llvm/Target/ |
D | Target.td | 101 // RegAltNameIndices - The alternate name indices which are valid for this 103 list<RegAltNameIndex> RegAltNameIndices = [];
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
D | Target.td | 154 // RegAltNameIndices - The alternate name indices which are valid for this 156 list<RegAltNameIndex> RegAltNameIndices = [];
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/external/llvm-project/llvm/include/llvm/Target/ |
D | Target.td | 154 // RegAltNameIndices - The alternate name indices which are valid for this 156 list<RegAltNameIndex> RegAltNameIndices = [];
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