| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 39 RegBase, enumerator
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
64 if (BaseType == X86AddressMode::RegBase) in getFullAddress()
93 AM.BaseType = X86AddressMode::RegBase; in getAddressFromInstr()
155 if (AM.BaseType == X86AddressMode::RegBase) in addFullAddress()
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| D | X86ISelDAGToDAG.cpp | 53 RegBase, enumerator
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
91 if (BaseType != RegBase) return false; in isRIPRelative()
99 BaseType = RegBase; in setBaseReg()
845 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
857 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
888 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAdd()
1166 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
1243 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
1314 if ((AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 44 RegBase, enumerator
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
68 if (BaseType == X86AddressMode::RegBase) in getFullAddress()
97 AM.BaseType = X86AddressMode::RegBase; in getAddressFromInstr()
176 if (AM.BaseType == X86AddressMode::RegBase) in addFullAddress()
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| D | X86ISelDAGToDAG.cpp | 59 RegBase, enumerator
82 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
98 if (BaseType != RegBase) return false; in isRIPRelative()
106 BaseType = RegBase; in setBaseReg()
1726 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
1741 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
1775 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAdd()
2147 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
2223 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
2295 if ((AM.BaseType == X86ISelAddressMode::RegBase && AM.Base_Reg.getNode() && in matchAddressRecursively()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 44 RegBase, enumerator
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
68 if (BaseType == X86AddressMode::RegBase) in getFullAddress()
97 AM.BaseType = X86AddressMode::RegBase; in getAddressFromInstr()
176 if (AM.BaseType == X86AddressMode::RegBase) in addFullAddress()
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| D | X86ISelDAGToDAG.cpp | 57 RegBase, enumerator
80 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
96 if (BaseType != RegBase) return false; in isRIPRelative()
104 BaseType = RegBase; in setBaseReg()
1547 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
1562 AM.BaseType == X86ISelAddressMode::RegBase && in matchAddress()
1595 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAdd()
1967 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
2043 if (AM.BaseType == X86ISelAddressMode::RegBase && in matchAddressRecursively()
2115 if ((AM.BaseType == X86ISelAddressMode::RegBase && AM.Base_Reg.getNode() && in matchAddressRecursively()
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 38 RegBase, enumerator
56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr), in MSP430ISelAddressMode()
66 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) { in dump()
168 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { in MatchAddressBase()
174 AM.BaseType = MSP430ISelAddressMode::RegBase; in MatchAddressBase()
196 if (AM.BaseType == MSP430ISelAddressMode::RegBase in MatchAddress()
251 if (AM.BaseType == MSP430ISelAddressMode::RegBase) { in SelectAddr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 38 RegBase, enumerator
40 } BaseType = RegBase;
64 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) { in dump()
169 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { in MatchAddressBase()
175 AM.BaseType = MSP430ISelAddressMode::RegBase; in MatchAddressBase()
197 if (AM.BaseType == MSP430ISelAddressMode::RegBase in MatchAddress()
251 if (AM.BaseType == MSP430ISelAddressMode::RegBase) in SelectAddr()
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| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 38 RegBase, enumerator
40 } BaseType = RegBase;
64 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) { in dump()
169 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { in MatchAddressBase()
175 AM.BaseType = MSP430ISelAddressMode::RegBase; in MatchAddressBase()
197 if (AM.BaseType == MSP430ISelAddressMode::RegBase in MatchAddress()
251 if (AM.BaseType == MSP430ISelAddressMode::RegBase) in SelectAddr()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 50 typedef enum { RegBase, FrameIndexBase } BaseKind; enumerator
65 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; } in Address()
68 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 52 using BaseKind = enum { RegBase, FrameIndexBase };
55 BaseKind Kind = RegBase;
76 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 52 using BaseKind = enum { RegBase, FrameIndexBase };
55 BaseKind Kind = RegBase;
73 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 44 typedef enum { RegBase, FrameIndexBase } BaseKind; enumerator
59 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; } in Address()
62 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
1203 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 87 using BaseKind = enum { RegBase, FrameIndexBase };
90 BaseKind Kind = RegBase;
106 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
1262 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 87 using BaseKind = enum { RegBase, FrameIndexBase };
90 BaseKind Kind = RegBase;
106 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
1260 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 69 RegBase, enumerator
82 : BaseType(RegBase), Offset(0) { in Address()
447 Addr.BaseType = Address::RegBase; in PPCSimplifyAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 91 RegBase, enumerator
93 } BaseType = RegBase;
858 Addr.BaseType = Address::RegBase; in ARMSimplifyAddress()
2022 Addr.BaseType = Address::RegBase; in ProcessCallArgs()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 90 RegBase, enumerator
92 } BaseType = RegBase;
845 Addr.BaseType = Address::RegBase; in ARMSimplifyAddress()
2009 Addr.BaseType = Address::RegBase; in ProcessCallArgs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 55 RegBase, enumerator
68 : BaseType(RegBase), Offset(0) { in Address()
862 Addr.BaseType = Address::RegBase; in ARMSimplifyAddress()
2004 Addr.BaseType = Address::RegBase; in ProcessCallArgs()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 68 RegBase, enumerator
81 : BaseType(RegBase), Offset(0) { in Address()
440 Addr.BaseType = Address::RegBase; in PPCSimplifyAddress()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 68 RegBase, enumerator
81 : BaseType(RegBase), Offset(0) { in Address()
439 Addr.BaseType = Address::RegBase; in PPCSimplifyAddress()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 48 RegBase, enumerator
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend), in Address()
71 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
983 Addr.setKind(Address::RegBase); in simplifyAddress()
3005 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 83 RegBase,
88 BaseKind Kind = RegBase;
106 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
1060 Addr.setKind(Address::RegBase); in simplifyAddress()
3134 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 83 RegBase,
88 BaseKind Kind = RegBase;
106 bool isRegBase() const { return Kind == RegBase; } in isRegBase()
1062 Addr.setKind(Address::RegBase); in simplifyAddress()
3136 Addr.setKind(Address::RegBase); in processCallArgs()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 6357 Variable *RegBase = nullptr; in legalize() local
6360 RegBase = llvm::cast<Variable>( in legalize()
6378 if (Base != RegBase || Index != RegIndex) { in legalize()
6382 Mem = OperandARM32Mem::create(Func, Ty, RegBase, RegIndex, in legalize()
6386 Mem = OperandARM32Mem::create(Func, Ty, RegBase, Offset, in legalize()
|