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Searched refs:RegClass (Results 1 – 25 of 192) sorted by relevance

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/external/mesa3d/src/amd/compiler/
Daco_ir.h253 struct RegClass { struct
283 RegClass() = default;
284 constexpr RegClass(RC rc) in RegClass() argument
286 constexpr RegClass(RegType type, unsigned size) in RegClass() function
298 constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); } in as_linear() argument
299 constexpr RegClass as_subdword() const { return RegClass((RC) (rc | 1 << 7)); } in as_subdword() argument
301 static constexpr RegClass get(RegType type, unsigned bytes) { in get() argument
303 return RegClass(type, DIV_ROUND_UP(bytes, 4u)); in get()
305 return bytes % 4u ? RegClass(type, bytes).as_subdword() : in get()
306 RegClass(type, bytes / 4u); in get()
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Daco_print_ir.cpp60 static void print_reg_class(const RegClass rc, FILE *output) in print_reg_class()
63 case RegClass::s1: fprintf(output, " s1: "); return; in print_reg_class()
64 case RegClass::s2: fprintf(output, " s2: "); return; in print_reg_class()
65 case RegClass::s3: fprintf(output, " s3: "); return; in print_reg_class()
66 case RegClass::s4: fprintf(output, " s4: "); return; in print_reg_class()
67 case RegClass::s6: fprintf(output, " s6: "); return; in print_reg_class()
68 case RegClass::s8: fprintf(output, " s8: "); return; in print_reg_class()
69 case RegClass::s16: fprintf(output, "s16: "); return; in print_reg_class()
70 case RegClass::v1: fprintf(output, " v1: "); return; in print_reg_class()
71 case RegClass::v2: fprintf(output, " v2: "); return; in print_reg_class()
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Daco_lower_to_hw_instr.cpp312 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1; in emit_int64_op()
407 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
445 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
447 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
950 RegClass def_cls = bytes % 4 == 0 ? RegClass(src.def.regClass().type(), bytes / 4u) : in split_copy()
951 RegClass(src.def.regClass().type(), bytes).as_subdword(); in split_copy()
964 RegClass op_cls = bytes % 4 == 0 ? RegClass(src.op.regClass().type(), bytes / 4u) : in split_copy()
965 RegClass(src.op.regClass().type(), bytes).as_subdword(); in split_copy()
1094 … Definition lo_half = Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
1095 … Definition dst = Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes())); in do_copy()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp33 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
35 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
88 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
91 if (!RegClass) { in constrainOperandRegClass()
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
/external/llvm-project/llvm/test/TableGen/
Dget-operand-type.td14 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
19 def RegOp : RegisterOperand<RegClass>;
41 let OutOperandList = (outs RegClass:$d);
51 // CHECK-NEXT: OpTypes::RegClass, OpTypes::RegOp,
DRegisterEncoder.td15 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
17 def RegOperand : RegisterOperand<RegClass> {
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
78 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h114 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
143 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
146 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
DRegisterClassInfo.h45 std::unique_ptr<RCInfo[]> RegClass; variable
71 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/external/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
232 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
/external/llvm-project/llvm/lib/CodeGen/
DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp39 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
40 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
41 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
50 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { in constrainOperandRegClass() argument
55 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
93 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
102 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
103 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
105 if (!RegClass) { in constrainOperandRegClass()
121 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td563 /// RegClass - This is the register class associated with this type. For
565 RegisterClass RegClass = regclass;
658 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
668 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
675 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
676 [(set typeinfo.RegClass:$dst, EFLAGS,
677 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
684 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
685 [(set typeinfo.RegClass:$dst, EFLAGS,
686 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
660 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
610 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
611 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
614 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
120 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/external/swiftshader/third_party/subzero/src/
DIceTypes.h36 enum RegClass : uint8_t { enum
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
/external/llvm-project/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
74 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
74 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
107 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
110 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
113 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
118 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
123 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
645 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
646 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
647 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
650 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
126 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrArithmetic.td552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
660 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
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