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Searched refs:RegClasses (Results 1 – 8 of 8) sorted by relevance

/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp946 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
949 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
951 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
957 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { in computeSubClasses()
974 for (auto &RC : RegClasses) { in computeSubClasses()
976 auto I = RegClasses.begin(); in computeSubClasses()
990 for (auto &RC : RegClasses) in computeSubClasses()
1009 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs() local
1018 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs()
1028 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs()
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DCodeGenRegisters.h556 std::list<CodeGenRegisterClass> RegClasses; variable
594 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
715 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
718 return RegClasses; in getRegClasses()
DCodeGenTarget.cpp284 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace() local
285 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; in getRegNamespace()
348 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg() local
352 for (CodeGenRegisterClass &RC : RegClasses) { in getSuperRegForSubReg()
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp851 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
854 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
856 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
860 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { in computeSubClasses()
877 for (auto &RC : RegClasses) { in computeSubClasses()
879 auto I = RegClasses.begin(); in computeSubClasses()
893 for (auto &RC : RegClasses) in computeSubClasses()
996 RegClasses.emplace_back(*this, RC); in CodeGenRegBank()
997 addToMaps(&RegClasses.back()); in CodeGenRegBank()
1004 RegClasses.sort(TopoOrderRC); in CodeGenRegBank()
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DCodeGenRegisters.h502 std::list<CodeGenRegisterClass> RegClasses; variable
536 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
652 return RegClasses; in getRegClasses()
/external/llvm-project/llvm/include/llvm/Target/
DTargetSchedule.td477 // a list of register classes (see field `RegClasses`). An empty list of
481 // A register R can be renamed if its register class appears in the `RegClasses`
486 // However, V is only renamed if its register class is part of `RegClasses`.
497 // register class that is in `RegClasses`.
539 list<RegisterClass> RegClasses = Classes;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSchedule.td477 // a list of register classes (see field `RegClasses`). An empty list of
481 // A register R can be renamed if its register class appears in the `RegClasses`
486 // However, V is only renamed if its register class is part of `RegClasses`.
497 // register class that is in `RegClasses`.
539 list<RegisterClass> RegClasses = Classes;
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.cpp1548 const RegClassType RegClasses[] = { in addProlog() local
1553 for (const auto &RegClass : RegClasses) { in addProlog()