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Searched refs:RegDef (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/lib/MCA/Stages/
DDispatchStage.cpp48 for (const WriteState &RegDef : IR.getInstruction()->getDefs()) in checkPRF() local
49 RegDefs.emplace_back(RegDef.getRegisterID()); in checkPRF()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/
DDispatchStage.cpp48 for (const WriteState &RegDef : IR.getInstruction()->getDefs()) in checkPRF() local
49 RegDefs.emplace_back(RegDef.getRegisterID()); in checkPRF()
/external/llvm/lib/CodeGen/
DImplicitNullChecks.cpp233 for (auto &RegDef : RegDefs) { in isSafeToHoist() local
234 unsigned Reg = RegDef.first; in isSafeToHoist()
235 MachineInstr *MI = RegDef.second; in isSafeToHoist()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp640 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in areCalleeOutgoingArgsTailCallable() local
641 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) { in areCalleeOutgoingArgsTailCallable()
649 Register CopyRHS = RegDef->getOperand(1).getReg(); in areCalleeOutgoingArgsTailCallable()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp665 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in areCalleeOutgoingArgsTailCallable() local
666 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) { in areCalleeOutgoingArgsTailCallable()
674 Register CopyRHS = RegDef->getOperand(1).getReg(); in areCalleeOutgoingArgsTailCallable()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp74 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass() local
75 Observer->changedInstr(*RegDef); in constrainOperandRegClass()
/external/llvm-project/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp333 const MachineOperand *RegDef = MRI.getOneDef(Reg); in isSSA() local
334 if (RegDef && RegDef->getSubReg() != 0) in isSSA()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp535 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef; in ReleasePredecessors() local
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) && in ReleasePredecessors()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp563 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors() local
564 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
DFastISel.cpp168 Register RegDef; in findSinkableLocalRegDef() local
173 if (RegDef) in findSinkableLocalRegDef()
175 RegDef = MO.getReg(); in findSinkableLocalRegDef()
181 return RegDef; in findSinkableLocalRegDef()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp563 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors() local
564 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
DFastISel.cpp169 unsigned RegDef = 0; in findSinkableLocalRegDef() local
174 if (RegDef) in findSinkableLocalRegDef()
176 RegDef = MO.getReg(); in findSinkableLocalRegDef()
182 return RegDef; in findSinkableLocalRegDef()