Home
last modified time | relevance | path

Searched refs:RegIdx (Results 1 – 25 of 51) sorted by relevance

123

/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp114 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
115 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
117 WorklistMembers.set(RegIdx); in PutInWorklist()
118 Worklist.push_back(RegIdx); in PutInWorklist()
366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in determineInitialDefinedLanes() local
367 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
368 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
499 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
500 unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); in runOnce()
503 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
[all …]
DSplitKit.cpp384 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
390 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
397 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), in defValue()
420 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { in forceRecompute() argument
422 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; in forceRecompute()
435 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in forceRecompute()
441 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument
448 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
452 bool Late = RegIdx != 0; in defFromParent()
455 unsigned Original = VRM.getOriginal(Edit->get(RegIdx)); in defFromParent()
[all …]
DSplitKit.h324 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument
325 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc()
333 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
339 void forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI);
343 VNInfo *defFromParent(unsigned RegIdx,
DLiveVariables.cpp85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument
86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && in getVarInfo()
88 VirtRegInfo.grow(RegIdx); in getVarInfo()
89 return VirtRegInfo[RegIdx]; in getVarInfo()
/external/llvm-project/llvm/lib/CodeGen/
DDetectDeadLanes.cpp109 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
110 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
112 WorklistMembers.set(RegIdx); in PutInWorklist()
113 Worklist.push_back(RegIdx); in PutInWorklist()
360 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
361 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
362 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
493 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
494 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
497 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
[all …]
DSplitKit.cpp459 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
466 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
475 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); in defValue()
496 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute() argument
497 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute()
509 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); in forceRecompute()
543 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
556 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); in buildCopy()
630 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument
636 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
[all …]
DSplitKit.h344 LiveIntervalCalc &getLICalc(unsigned RegIdx) { in getLICalc() argument
345 return LICalc[SpillMode != SM_Partition && RegIdx != 0]; in getLICalc()
377 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx,
384 void forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI);
392 VNInfo *defFromParent(unsigned RegIdx,
444 bool Late, unsigned RegIdx);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp112 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
113 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
115 WorklistMembers.set(RegIdx); in PutInWorklist()
116 Worklist.push_back(RegIdx); in PutInWorklist()
363 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
364 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
365 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
496 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
497 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
500 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
[all …]
DSplitKit.cpp456 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
463 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
472 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); in defValue()
493 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute() argument
494 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute()
506 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); in forceRecompute()
540 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
553 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); in buildCopy()
627 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument
633 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
[all …]
DSplitKit.h343 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument
344 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc()
369 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx,
376 void forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI);
384 VNInfo *defFromParent(unsigned RegIdx,
436 bool Late, unsigned RegIdx);
DLiveVariables.cpp85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument
86 assert(Register::isVirtualRegister(RegIdx) && in getVarInfo()
88 VirtRegInfo.grow(RegIdx); in getVarInfo()
89 return VirtRegInfo[RegIdx]; in getVarInfo()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp626 struct RegIdxOp RegIdx; member
640 Op->RegIdx.Index = Index; in CreateReg()
641 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
642 Op->RegIdx.Kind = RegKind; in CreateReg()
652 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
653 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
655 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
661 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
663 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPRMM16Reg()
669 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR64Reg()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.cpp203 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
249 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
/external/llvm/lib/Target/ARM/
DARMCallingConv.h210 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
251 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
253 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.cpp201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
248 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
250 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
253 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp879 struct RegIdxOp RegIdx; member
894 Op->RegIdx.Index = Index; in CreateReg()
895 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
896 Op->RegIdx.Kind = RegKind; in CreateReg()
897 Op->RegIdx.Tok.Data = Str.data(); in CreateReg()
898 Op->RegIdx.Tok.Length = Str.size(); in CreateReg()
908 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
909 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
917 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp863 struct RegIdxOp RegIdx; member
878 Op->RegIdx.Index = Index; in CreateReg()
879 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
880 Op->RegIdx.Kind = RegKind; in CreateReg()
881 Op->RegIdx.Tok.Data = Str.data(); in CreateReg()
882 Op->RegIdx.Tok.Length = Str.size(); in CreateReg()
892 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
893 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
895 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
901 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
[all …]
/external/llvm-project/llvm/lib/Target/AVR/
DAVRAsmPrinter.cpp115 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
116 assert(RegIdx < NumOpRegs && "Multibyte index out of range."); in PrintAsmOperand()
118 Reg = MI->getOperand(OpNum + RegIdx).getReg(); in PrintAsmOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRAsmPrinter.cpp115 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
116 assert(RegIdx < NumOpRegs && "Multibyte index out of range."); in PrintAsmOperand()
118 Reg = MI->getOperand(OpNum + RegIdx).getReg(); in PrintAsmOperand()
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp236 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); in printRegOperand() local
275 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. in printRegOperand()
279 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen. in printRegOperand()
286 O << RegIdx; in printRegOperand()
290 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; in printRegOperand()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp529 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction() local
530 if (RegIdx >= 0) in runOnMachineFunction()
531 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp517 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction() local
518 if (RegIdx >= 0) in runOnMachineFunction()
519 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction()
/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp72 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
73 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) { in getMSACtrlReg()
821 SDValue RegIdx = Node->getOperand(2); in trySelect() local
823 getMSACtrlReg(RegIdx), MVT::i32); in trySelect()
854 SDValue RegIdx = Node->getOperand(2); in trySelect() local
857 getMSACtrlReg(RegIdx), Value); in trySelect()
/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp615 int RegIdx = BaseRegIdx + Offset; in computeIndirectRegAndOffset() local
616 if (RegIdx < 0) { in computeIndirectRegAndOffset()
617 Offset = RegIdx; in computeIndirectRegAndOffset()
618 RegIdx = 0; in computeIndirectRegAndOffset()
623 unsigned Reg = RC->getRegister(RegIdx); in computeIndirectRegAndOffset()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); in getMSACtrlReg()
842 SDValue RegIdx = Node->getOperand(2); in trySelect() local
844 getMSACtrlReg(RegIdx), MVT::i32); in trySelect()
875 SDValue RegIdx = Node->getOperand(2); in trySelect() local
878 getMSACtrlReg(RegIdx), Value); in trySelect()

123