/external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
D | RegisterAliasing.cpp | 14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits() argument 16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits() 19 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid(); in getAliasedBits() 27 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo) in RegisterAliasingTracker() argument 28 : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()), in RegisterAliasingTracker() 29 Origins(RegInfo.getNumRegs()) {} in RegisterAliasingTracker() 32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker() argument 34 : RegisterAliasingTracker(RegInfo) { in RegisterAliasingTracker() 38 FillOriginAndAliasedBits(RegInfo, SourceBits); in RegisterAliasingTracker() 41 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo, in RegisterAliasingTracker() argument [all …]
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D | RegisterAliasing.h | 28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, 43 RegisterAliasingTracker(const MCRegisterInfo &RegInfo, 48 RegisterAliasingTracker(const MCRegisterInfo &RegInfo, 64 RegisterAliasingTracker(const MCRegisterInfo &RegInfo); 67 void FillOriginAndAliasedBits(const MCRegisterInfo &RegInfo, 78 RegisterAliasingTrackerCache(const MCRegisterInfo &RegInfo, 88 const MCRegisterInfo ®Info() const { return RegInfo; } in regInfo() 97 const MCRegisterInfo &RegInfo; 114 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs);
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/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
D | RegisterAliasingTest.cpp | 28 const auto &RegInfo = State.getRegInfo(); in TEST_F() local 29 const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64); in TEST_F() 44 const auto &RegInfo = State.getRegInfo(); in TEST_F() local 45 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F() 48 RegInfo, NoReservedReg, in TEST_F() 49 RegInfo.getRegClass( in TEST_F() 52 BitVector sum(RegInfo.getNumRegs()); in TEST_F() 53 sum |= RegisterAliasingTracker(RegInfo, Mips::ZERO_64).aliasedBits(); in TEST_F() 54 sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits(); in TEST_F() 55 sum |= RegisterAliasingTracker(RegInfo, Mips::V1_64).aliasedBits(); in TEST_F() [all …]
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/external/llvm-project/llvm/unittests/tools/llvm-exegesis/X86/ |
D | RegisterAliasingTest.cpp | 29 const auto &RegInfo = State.getRegInfo(); in TEST_F() local 30 const RegisterAliasingTracker tracker(RegInfo, X86::EAX); in TEST_F() 45 const auto &RegInfo = State.getRegInfo(); in TEST_F() local 46 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F() 49 RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID)); in TEST_F() 51 BitVector sum(RegInfo.getNumRegs()); in TEST_F() 52 sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits(); in TEST_F() 53 sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits(); in TEST_F() 54 sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits(); in TEST_F() 55 sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits(); in TEST_F() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVRegisterInfo.td | 101 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 107 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 122 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 135 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 144 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 157 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 163 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local 144 RegInfo->needsStackRealignment(MF); in hasFP() 254 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in findScratchNonCalleeSaveRegister() local 255 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MF); in findScratchNonCalleeSaveRegister() 276 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local 279 if (!RegInfo->needsStackRealignment(*MF)) in canUseAsPrologue() 291 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local 304 if (RegInfo->needsStackRealignment(MF)) in shouldCombineCSRLocalStackBump() 413 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in emitPrologue() local 499 const bool NeedsRealignment = RegInfo->needsStackRealignment(MF); in emitPrologue() [all …]
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in __anon5a2c0d880111::ExpandPseudo 102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo() 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() 177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond() 188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() 194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond() 206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC() 211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC() 215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in __anon6e96727c0111::ExpandPseudo 102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo() 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() 177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond() 188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() 194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond() 206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC() 211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC() 215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC() [all …]
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/external/llvm/lib/Target/ARM/ |
D | Thumb1FrameLowering.cpp | 56 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr() 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr() 92 const ThumbRegisterInfo *RegInfo = in emitPrologue() local 107 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue() 108 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue() 121 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue() 133 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), in emitPrologue() 266 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue() 288 if (RegInfo->needsStackRealignment(MF)) in emitPrologue() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEFrameLowering.cpp | 75 const MipsRegisterInfo &RegInfo; member in __anond1dde3da0111::ExpandPseudo 83 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo() 154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() 158 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond() 169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() 175 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond() 187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() 191 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC() 192 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC() 196 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86CallFrameOptimization.cpp | 100 const X86RegisterInfo &RegInfo, 222 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local 224 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction() 261 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument 303 if (!RegInfo.isPhysicalRegister(Reg)) in classifyInstruction() 305 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction() 309 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction() 323 const X86RegisterInfo &RegInfo = in collectCallInfo() local 349 unsigned StackPtr = RegInfo.getStackRegister(); in collectCallInfo() 369 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) != in collectCallInfo() [all …]
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D | X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local 22 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer() 24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF); in setRestoreBasePointer()
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/external/llvm/lib/Target/Sparc/ |
D | SparcFrameLowering.cpp | 93 const SparcRegisterInfo &RegInfo = in emitPrologue() local 99 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue() 158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue() 171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue() 172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue() 234 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local 238 RegInfo->needsStackRealignment(MF) || in hasFP() 248 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local 266 } else if (RegInfo->needsStackRealignment(MF)) { in getFrameIndexReference() 280 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | Thumb1FrameLowering.cpp | 117 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local 135 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr() 138 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr() 152 const ThumbRegisterInfo *RegInfo = in emitPrologue() local 167 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue() 168 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue() 181 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue() 193 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue() 384 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue() 404 if (RegInfo->needsStackRealignment(MF)) { in emitPrologue() [all …]
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | Thumb1FrameLowering.cpp | 119 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local 137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr() 140 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr() 154 const ThumbRegisterInfo *RegInfo = in emitPrologue() local 169 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue() 170 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue() 183 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue() 195 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue() 386 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue() 406 if (RegInfo->needsStackRealignment(MF)) { in emitPrologue() [all …]
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/external/llvm-project/llvm/lib/Target/Sparc/ |
D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = in emitPrologue() local 100 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue() 156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue() 169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue() 170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue() 251 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local 255 RegInfo->needsStackRealignment(MF) || in hasFP() 265 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local 283 } else if (RegInfo->needsStackRealignment(MF)) { in getFrameIndexReference() 297 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = in emitPrologue() local 100 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue() 158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue() 171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue() 172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue() 252 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local 256 RegInfo->needsStackRealignment(MF) || in hasFP() 266 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local 284 } else if (RegInfo->needsStackRealignment(MF)) { in getFrameIndexReference() 298 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 240 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local 251 RegInfo->needsStackRealignment(MF)) in hasFP() 421 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local 424 if (!RegInfo->needsStackRealignment(*MF)) in canUseAsPrologue() 453 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local 466 if (RegInfo->needsStackRealignment(MF)) in shouldCombineCSRLocalStackBump() 496 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in InsertSEH() local 505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() 506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() 526 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86CallFrameOptimization.cpp | 113 const X86RegisterInfo &RegInfo, 242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local 244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction() 281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument 341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction() 345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction() 359 const X86RegisterInfo &RegInfo = in collectCallInfo() local 383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo() 415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86CallFrameOptimization.cpp | 114 const X86RegisterInfo &RegInfo, 242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local 244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction() 281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument 341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction() 345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction() 359 const X86RegisterInfo &RegInfo = in collectCallInfo() local 383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo() 415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
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/external/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 107 const VRegInfo &RegInfo) const; 303 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local 304 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep() 309 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep() 462 const VRegInfo &RegInfo) const { in isUndefRegAtInput() 465 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask) == 0; in isUndefRegAtInput() 548 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local 549 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes == 0) { in runOnce() 555 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
D | ControlHeightReduction.cpp | 163 struct RegInfo { struct 164 RegInfo() : R(nullptr), HasBranch(false) {} in RegInfo() argument 165 RegInfo(Region *RegionIn) : R(RegionIn), HasBranch(false) {} in RegInfo() function 178 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope() 224 for (RegInfo &RI : Next->RegInfos) in append() 233 for (RegInfo &RI : RegInfos) in addSub() 250 [&Boundary](const RegInfo& RI) { in split() 255 SmallVector<RegInfo, 8> TailRegInfos; in split() 260 for (RegInfo &RI : TailRegInfos) in split() 271 [&Parent](const RegInfo& RI) { in split() [all …]
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/external/llvm-project/llvm/lib/Transforms/Instrumentation/ |
D | ControlHeightReduction.cpp | 163 struct RegInfo { struct 164 RegInfo() : R(nullptr), HasBranch(false) {} in RegInfo() function 165 RegInfo(Region *RegionIn) : R(RegionIn), HasBranch(false) {} in RegInfo() argument 178 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope() 231 for (RegInfo &RI : RegInfos) in addSub() 248 RegInfos, [&Boundary](const RegInfo &RI) { return Boundary == RI.R; }); in split() 251 ArrayRef<RegInfo> TailRegInfos(BoundaryIt, RegInfos.end()); in split() 253 for (const RegInfo &RI : TailRegInfos) in split() 264 [&Parent](const RegInfo &RI) { in split() 281 for (const RegInfo &RI : RegInfos) in contains() [all …]
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/external/llvm-project/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 102 const VRegInfo &RegInfo) const; 297 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local 298 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep() 303 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep() 456 const VRegInfo &RegInfo) const { in isUndefRegAtInput() 459 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput() 540 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local 541 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in runOnce() 548 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 105 const VRegInfo &RegInfo) const; 300 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local 301 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep() 306 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep() 459 const VRegInfo &RegInfo) const { in isUndefRegAtInput() 462 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput() 543 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local 544 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in runOnce() 551 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
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