| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 78 unsigned &RegKind);
781 unsigned RegNo, RegKind; in parseOperand() local
782 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
787 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
841 unsigned RegKind; in parseSparcAsmOperand() local
842 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
848 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
936 unsigned &RegKind) in matchRegisterName() argument
940 RegKind = SparcOperand::rk_None; in matchRegisterName()
947 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 97 unsigned &RegKind);
824 unsigned RegNo, RegKind; in parseOperand() local
825 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
830 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
883 unsigned RegKind; in parseSparcAsmOperand() local
884 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
890 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
983 unsigned &RegKind) { in matchRegisterName() argument
986 RegKind = SparcOperand::rk_None; in matchRegisterName()
993 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
[all …]
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| /external/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 99 unsigned &RegKind);
835 unsigned RegNo, RegKind; in parseOperand() local
836 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
841 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
894 unsigned RegKind; in parseSparcAsmOperand() local
895 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
901 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
994 unsigned &RegKind) { in matchRegisterName() argument
997 RegKind = SparcOperand::rk_None; in matchRegisterName()
1004 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
[all …]
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 99 unsigned RegKind : 4; member
165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
170 Op->Mem.RegKind = RegKind; in createMem()
199 bool isReg(RegisterKind RegKind) const { in isReg()
200 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
242 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 118 unsigned RegKind : 4; member
184 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
189 Op->Mem.RegKind = RegKind; in createMem()
222 bool isReg(RegisterKind RegKind) const { in isReg()
223 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
263 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
264 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
266 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
269 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 64 enum class RegKind { enum
82 StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
156 unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
198 RegKind MatchKind);
223 template <RegKind VectorKind>
312 RegKind Kind;
341 RegKind RegisterKind;
1027 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
1031 return Kind == k_Register && Reg.Kind == RegKind::NeonVector; in isNeonVectorReg()
1035 return Kind == k_Register && Reg.Kind == RegKind::NeonVector && in isNeonVectorRegLo()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 65 enum class RegKind { enum
83 StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
157 unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
230 RegKind MatchKind);
255 template <RegKind VectorKind>
346 RegKind Kind;
375 RegKind RegisterKind;
1066 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
1070 return Kind == k_Register && Reg.Kind == RegKind::NeonVector; in isNeonVectorReg()
1074 return Kind == k_Register && Reg.Kind == RegKind::NeonVector && in isNeonVectorRegLo()
[all …]
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| /external/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 116 unsigned RegKind : 4; member
182 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
187 Op->Mem.RegKind = RegKind; in createMem()
220 bool isReg(RegisterKind RegKind) const { in isReg()
221 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
261 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
262 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
264 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
265 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
267 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 987 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister() argument
988 switch (RegKind) { in usesRegister()
1064 RegisterKind RegKind, unsigned Reg1);
1065 bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
1067 unsigned ParseRegularReg(RegisterKind &RegKind,
1070 unsigned ParseSpecialReg(RegisterKind &RegKind,
1073 unsigned ParseRegList(RegisterKind &RegKind,
1077 unsigned getRegularReg(RegisterKind RegKind,
1083 Optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
1084 void initializeGprCountSymbol(RegisterKind RegKind);
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1030 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister() argument
1031 switch (RegKind) { in usesRegister()
1107 RegisterKind RegKind, unsigned Reg1, SMLoc Loc);
1108 bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1111 bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1114 unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1117 unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1120 unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1123 unsigned getRegularReg(RegisterKind RegKind,
1130 Optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 586 …bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1,…
587 …bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidt…
804 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind… in AddNextRegisterToList() argument
806 switch (RegKind) { in AddNextRegisterToList()
825 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, u… in ParseAMDGPURegister() argument
832 RegKind = IS_SPECIAL; in ParseAMDGPURegister()
837 RegKind = IS_VGPR; in ParseAMDGPURegister()
840 RegKind = IS_SGPR; in ParseAMDGPURegister()
843 RegKind = IS_TTMP; in ParseAMDGPURegister()
886 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) in ParseAMDGPURegister()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.h | 29 enum RegKind { enum
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.h | 37 enum RegKind { enum
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 531 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
543 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
553 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
979 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
981 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 515 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
527 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
537 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
958 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
960 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 331 bool validateMSAIndex(int Val, int RegKind);
562 enum RegKind { enum in __anonf9177d9b0311::MipsOperand
607 RegKind Kind; /// Bitfield of the kinds it could possibly be
635 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, in CreateReg() argument
642 Op->RegIdx.Kind = RegKind; in CreateReg()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 9990 DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
9997 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 16, 8>());
10004 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 1, 64>());
10011 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 64>());
10018 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 2, 32>());
10025 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 16>());
10032 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 4, 32>());
10039 DiagnosticPredicate DP(Operand.isImplicitlyTypedVectorList<RegKind::NeonVector, 4>());
10046 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 8>());
10053 DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::NeonVector, 4, 8, 16>());
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 448 bool validateMSAIndex(int Val, int RegKind);
800 enum RegKind { enum in __anonea9ece490211::MipsOperand
859 RegKind Kind; /// Bitfield of the kinds it could possibly be
889 RegKind RegKind, in CreateReg() argument
896 Op->RegIdx.Kind = RegKind; in CreateReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 432 bool validateMSAIndex(int Val, int RegKind);
784 enum RegKind { enum in __anon46da8d3d0211::MipsOperand
843 RegKind Kind; /// Bitfield of the kinds it could possibly be
873 RegKind RegKind, in CreateReg() argument
880 Op->RegIdx.Kind = RegKind; in CreateReg()
|