Home
last modified time | relevance | path

Searched refs:RegNum (Results 1 – 25 of 127) sorted by relevance

123456

/external/swiftshader/third_party/subzero/src/
DIceRegistersMIPS32.h68 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
69 assert(int(Reg_GPR_First) <= int(RegNum)); in getEncodedGPR()
70 assert(unsigned(RegNum) <= Reg_GPR_Last); in getEncodedGPR()
71 return GPRRegister(RegNum - Reg_GPR_First); in getEncodedGPR()
74 static inline bool isGPRReg(RegNumT RegNum) { in isGPRReg() argument
75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) && in isGPRReg()
76 (unsigned(RegNum) <= Reg_GPR_Last)) || in isGPRReg()
77 ((int(Reg_I64PAIR_First) <= int(RegNum)) && in isGPRReg()
78 (unsigned(RegNum) <= Reg_I64PAIR_Last)); in isGPRReg()
82 static inline FPRRegister getEncodedFPR(RegNumT RegNum) { in getEncodedFPR() argument
[all …]
DIceRegistersARM32.h105 static inline void assertValidRegNum(RegNumT RegNum) { in assertValidRegNum() argument
106 (void)RegNum; in assertValidRegNum()
107 assert(RegNum.hasValue()); in assertValidRegNum()
110 static inline bool isGPRegister(RegNumT RegNum) { in isGPRegister() argument
111 RegNum.assertIsValid(); in isGPRegister()
112 return RegTable[RegNum].IsGPR; in isGPRegister()
125 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
126 RegNum.assertIsValid(); in getEncodedGPR()
127 return GPRRegister(RegTable[RegNum].Encoding); in getEncodedGPR()
140 static inline bool isGPR(RegNumT RegNum) { in isGPR() argument
[all …]
DIceTargetLoweringX8664Traits.h303 static const char *getRegName(RegNumT RegNum) { in getRegName()
312 RegNum.assertIsValid(); in getRegName()
313 return RegNames[RegNum]; in getRegName()
316 static GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR()
325 RegNum.assertIsValid(); in getEncodedGPR()
326 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
327 return GPRRegs[RegNum]; in getEncodedGPR()
330 static ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg()
339 RegNum.assertIsValid(); in getEncodedByteReg()
340 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
[all …]
DIceTargetLoweringX8632Traits.h278 static const char *getRegName(RegNumT RegNum) { in getRegName()
287 RegNum.assertIsValid(); in getRegName()
288 return RegNames[RegNum]; in getRegName()
291 static GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR()
300 RegNum.assertIsValid(); in getEncodedGPR()
301 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
302 return GPRRegs[RegNum]; in getEncodedGPR()
305 static ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg()
314 RegNum.assertIsValid(); in getEncodedByteReg()
315 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
[all …]
DIceTargetLoweringX8664.cpp294 void TargetX8664::_push_reg(RegNumT RegNum) { in _push_reg() argument
295 if (Traits::isXmm(RegNum)) { in _push_reg()
296 Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32); in _push_reg()
305 } else if (RegNum != Traits::RegisterSet::Reg_rbp || !NeedSandboxing) { in _push_reg()
306 _push(getPhysicalRegister(RegNum, Traits::WordType)); in _push_reg()
312 void TargetX8664::_pop_reg(RegNumT RegNum) { in _pop_reg() argument
313 if (Traits::isXmm(RegNum)) { in _pop_reg()
314 Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32); in _pop_reg()
324 _pop(getPhysicalRegister(RegNum, Traits::WordType)); in _pop_reg()
347 const auto RegNum = Var->getRegNum(); in isAssignedToRspOrRbp() local
[all …]
DIceRegAlloc.cpp434 const RegNumT RegNum = *RegNumBVIter(Iter.RegMask).begin(); in addSpillFill() local
435 Iter.Cur->setRegNumTmp(RegNum); in addSpillFill()
436 Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType()); in addSpillFill()
621 const auto RegNum = Cur->getRegNum(); in allocatePrecoloredRegister() local
623 assert(Cur->getRegNumTmp() == RegNum); in allocatePrecoloredRegister()
626 const auto &Aliases = *RegAliases[RegNum]; in allocatePrecoloredRegister()
648 const RegNumT RegNum = in allocateFreeRegister() local
650 Iter.Cur->setRegNumTmp(RegNum); in allocateFreeRegister()
655 const auto &Aliases = *RegAliases[RegNum]; in allocateFreeRegister()
741 const auto RegNum = Item->getRegNumTmp(); in handleNoFreeRegisters() local
[all …]
DIceTargetLoweringX8632.h55 void _push_reg(RegNumT RegNum);
56 void _pop_reg(RegNumT RegNum);
/external/llvm-project/compiler-rt/lib/xray/
Dxray_mips64.cpp34 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x8); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, HigherTracingHookAddr); in patchSled()
113 RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
114 Address[7] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
[all …]
Dxray_mips.cpp33 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x4); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, LoTracingHookAddr); in patchSled()
112 Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, in patchSled()
114 Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9, in patchSled()
[all …]
/external/llvm-project/llvm/lib/MC/
DMCRegisterInfo.cpp68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
74 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
76 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() argument
88 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
90 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) in getDwarfRegNumFromDwarfEHRegNum()
106 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
74 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
76 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() argument
88 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
90 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) in getDwarfRegNumFromDwarfEHRegNum()
106 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
[all …]
/external/llvm/lib/MC/
DMCRegisterInfo.cpp61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
88 int MCRegisterInfo::getCodeViewRegNum(unsigned RegNum) const { in getCodeViewRegNum()
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
68 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
72 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
68 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
72 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
/external/llvm-project/llvm/lib/Target/AVR/AsmParser/
DAVRAsmParser.cpp207 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
209 return std::make_unique<AVROperand>(RegNum, S, E); in CreateReg()
218 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMemri() argument
219 return std::make_unique<AVROperand>(RegNum, Val, S, E); in CreateMemri()
339 int RegNum = matchFn(Name); in parseRegisterName() local
345 if (RegNum == AVR::NoRegister) { in parseRegisterName()
346 RegNum = matchFn(Name.lower()); in parseRegisterName()
348 if (RegNum == AVR::NoRegister) { in parseRegisterName()
349 RegNum = matchFn(Name.upper()); in parseRegisterName()
352 return RegNum; in parseRegisterName()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/AsmParser/
DAVRAsmParser.cpp205 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
207 return std::make_unique<AVROperand>(RegNum, S, E); in CreateReg()
216 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMemri() argument
217 return std::make_unique<AVROperand>(RegNum, Val, S, E); in CreateMemri()
337 int RegNum = matchFn(Name); in parseRegisterName() local
343 if (RegNum == AVR::NoRegister) { in parseRegisterName()
344 RegNum = matchFn(Name.lower()); in parseRegisterName()
346 if (RegNum == AVR::NoRegister) { in parseRegisterName()
347 RegNum = matchFn(Name.upper()); in parseRegisterName()
350 return RegNum; in parseRegisterName()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
DAVRInstPrinter.cpp89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, in getPrettyRegisterName() argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
98 return getRegisterName(RegNum); in getPrettyRegisterName()
/external/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
DAVRInstPrinter.cpp89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, in getPrettyRegisterName() argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
98 return getRegisterName(RegNum); in getPrettyRegisterName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp205 unsigned RegNum; member
252 return Reg.RegNum; in getReg()
429 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
431 Op->Reg.RegNum = RegNum; in CreateReg()
1767 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1768 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1770 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1775 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1784 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1785 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp184 unsigned RegNum; member
229 return Reg.RegNum; in getReg()
584 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg()
587 Op->Reg.RegNum = RegNum; in CreateReg()
1996 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1997 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
2000 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); in processInstruction()
2006 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); in processInstruction()
2015 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
2016 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp207 unsigned RegNum; member
254 return Reg.RegNum; in getReg()
433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
435 Op->Reg.RegNum = RegNum; in CreateReg()
1779 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1780 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1782 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1787 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1796 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1797 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/AsmParser/
DMSP430AsmParser.cpp197 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
199 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E); in CreateReg()
207 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, in CreateMem() argument
210 return std::make_unique<MSP430Operand>(RegNum, Val, S, E); in CreateMem()
213 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, in CreateIndReg() argument
215 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E); in CreateIndReg()
218 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, in CreatePostIndReg() argument
220 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); in CreatePostIndReg()
/external/llvm-project/llvm/lib/Target/MSP430/AsmParser/
DMSP430AsmParser.cpp199 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
201 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E); in CreateReg()
209 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, in CreateMem() argument
212 return std::make_unique<MSP430Operand>(RegNum, Val, S, E); in CreateMem()
215 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, in CreateIndReg() argument
217 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E); in CreateIndReg()
220 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, in CreatePostIndReg() argument
222 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); in CreatePostIndReg()
/external/llvm-project/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
123 unsigned RegNum; member
158 return Reg.RegNum; in getReg()
594 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, in createReg()
597 Op->Reg.RegNum = RegNum; in createReg()
698 unsigned RegNum; in parseRegister() local
705 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); in parseRegister()
706 if (RegNum == 0) { in parseRegister()
712 return LanaiOperand::createReg(RegNum, Start, End); in parseRegister()
719 bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, in ParseRegister() argument
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp345 unsigned RegNum; member
371 unsigned RegNum; member
575 return Reg.RegNum; in getReg()
585 return VectorList.RegNum; in getVectorListStart()
1076 Reg.RegNum) || in isNeonVectorRegLo()
1078 Reg.RegNum)); in isNeonVectorRegLo()
1153 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
1158 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum); in isGPR64as32()
1164 Reg.RegNum); in isWSeqPair()
1170 Reg.RegNum); in isXSeqPair()
[all …]

123456