| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 109 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in AddMachineRegPiece() local
111 if (PieceOffsetInBits == RegOffset) { in AddMachineRegPiece()
112 AddOpPiece(Size, RegOffset); in AddMachineRegPiece()
118 if (RegOffset) in AddMachineRegPiece()
119 AddShr(RegOffset); in AddMachineRegPiece()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 124 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in addMachineReg() local
127 setSubRegisterPiece(Size, RegOffset); in addMachineReg()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 430 unsigned RegOffset = in analyzeInst() local
435 unsigned Shift = ((NUM_VGPR_BANKS + Offset) - RegOffset); in analyzeInst()
438 unsigned Shift = (NUM_SGPR_BANKS + (Offset >> 1)) - (RegOffset >> 1); in analyzeInst()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 1026 int RegOffset = Offset->second; in generateCompactUnwindEncoding() local
1027 if (RegOffset != CurOffset - 4) { in generateCompactUnwindEncoding()
1030 << RegOffset << " but only supported at " in generateCompactUnwindEncoding()
|
| /external/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 125 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in addMachineReg() local
128 setSubRegisterPiece(Size, RegOffset); in addMachineReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 1222 int RegOffset = Offset->second; in generateCompactUnwindEncoding() local
1223 if (RegOffset != CurOffset - 4) { in generateCompactUnwindEncoding()
1226 << RegOffset << " but only supported at " in generateCompactUnwindEncoding()
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 1227 int RegOffset = Offset->second; in generateCompactUnwindEncoding() local
1228 if (RegOffset != CurOffset - 4) { in generateCompactUnwindEncoding()
1231 << RegOffset << " but only supported at " in generateCompactUnwindEncoding()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3698 SDValue Base, RegOffset, ImmOffset; in Select() local
3701 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3702 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select()
3708 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select()
3710 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select()
3727 SDValue Base, RegOffset, ImmOffset; in Select() local
3730 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3731 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select()
3737 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select()
3741 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 123 enum RegOffset { enum
|
| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 3765 llvm::Value *RegOffset = in EmitVAArg() local
3768 RegAddr.getPointer(), RegOffset), in EmitVAArg()
6024 llvm::Value *RegOffset = in EmitVAArg() local
6031 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset, in EmitVAArg()
|
| /external/llvm-project/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 4780 llvm::Value *RegOffset = in EmitVAArg() local
4783 RegAddr.getPointer(), RegOffset), in EmitVAArg()
7421 llvm::Value *RegOffset = in EmitVAArg() local
7427 Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset, in EmitVAArg()
|