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Searched refs:RegSizeInfo (Results 1 – 4 of 4) sorted by relevance

/external/llvm-project/llvm/utils/TableGen/
DInfoByHwMode.cpp122 RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) { in RegSizeInfo() function in RegSizeInfo
128 bool RegSizeInfo::operator< (const RegSizeInfo &I) const { in operator <()
133 bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const { in isSubClassOf()
139 void RegSizeInfo::writeToStream(raw_ostream &OS) const { in writeToStream()
148 auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)}); in RegSizeInfoByHwMode()
172 const RegSizeInfo &A0 = get(M0); in hasStricterSpillThan()
173 const RegSizeInfo &B0 = I.get(M0); in hasStricterSpillThan()
212 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) { in operator <<()
DInfoByHwMode.h148 struct RegSizeInfo { struct
153 RegSizeInfo(Record *R, const CodeGenHwModes &CGH); argument
154 RegSizeInfo() = default;
155 bool operator< (const RegSizeInfo &I) const;
156 bool operator== (const RegSizeInfo &I) const {
160 bool operator!= (const RegSizeInfo &I) const {
164 bool isSubClassOf(const RegSizeInfo &I) const;
168 struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
184 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
DRegisterInfoEmitter.cpp1294 const RegSizeInfo &RI = RC.RSI.get(M); in runTargetDesc()
DCodeGenRegisters.cpp797 RegSizeInfo RI; in CodeGenRegisterClass()