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Searched refs:RegType (Results 1 – 25 of 32) sorted by relevance

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/external/mesa3d/src/amd/compiler/
Daco_validate.cpp268 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
271 check(instr->definitions[0].getTemp().type() == RegType::vgpr, in validate_ir()
284 (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
288 … (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), in validate_ir()
296 … (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), in validate_ir()
299 (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
304 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { in validate_ir()
320 …check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU ins… in validate_ir()
322 check(op.isConstant() || op.regClass().type() <= RegType::sgpr, in validate_ir()
336 … if (op.isConstant() || (op.hasRegClass() && op.regClass().type() == RegType::sgpr)) in validate_ir()
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Daco_instruction_selection_setup.cpp315 RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, unsigned bitsize) in get_reg_class()
318 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
674 RegType type = RegType::sgpr; in init_context()
723 type = RegType::vgpr; in init_context()
739 … type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
742 … type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
746 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()
747 type = RegType::vgpr; in init_context()
759 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
767 RegType type = RegType::sgpr; in init_context()
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Daco_spill.cpp173 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in next_uses_per_block()
346 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in local_next_uses()
406 if (pair.first.type() == RegType::vgpr && in init_live_in_vars()
433 if (pair.first.type() == RegType::sgpr && in init_live_in_vars()
480 if (pair.first.type() == RegType::sgpr && in init_live_in_vars()
497 if (pair.first.type() == RegType::vgpr && in init_live_in_vars()
518 if (pair.first.type() == RegType::sgpr && in init_live_in_vars()
528 if (pair.first.type() == RegType::vgpr && in init_live_in_vars()
541 if (pair.first.type() == RegType::sgpr && in init_live_in_vars()
551 if (pair.first.type() == RegType::vgpr && in init_live_in_vars()
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Daco_ir.h246 enum class RegType { enum
286 constexpr RegClass(RegType type, unsigned size) in RegClass()
287 : rc((RC) ((type == RegType::vgpr ? 1 << 5 : 0) | size)) {} in RegClass()
292 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } in type()
301 static constexpr RegClass get(RegType type, unsigned bytes) { in get()
302 if (type == RegType::sgpr) { in get()
352 constexpr RegType type() const noexcept { return regClass().type(); } in type()
678 constexpr bool isOfType(RegType type) const noexcept in isOfType()
1428 if (t.type() == RegType::sgpr)
1455 if (t.type() == RegType::sgpr)
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Daco_instruction_selection.cpp254 if (val.type() == RegType::sgpr) { in as_vgpr()
256 return bld.copy(bld.def(RegType::vgpr, val.size()), val); in as_vgpr()
258 assert(val.type() == RegType::vgpr); in as_vgpr()
334 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr); in emit_extract_vector()
360 if (vec_src.type() == RegType::sgpr) { in emit_split_vector()
366 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); in emit_split_vector()
392 if (dst.type() == RegType::sgpr) in expand_vector()
408 if (dst.type() == RegType::sgpr) in expand_vector()
504 RegClass rc = RegClass(RegType::vgpr, component_size).as_subdword(); in byte_align_vector()
512 if (dst.type() == RegType::vgpr) { in byte_align_vector()
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Daco_reduce_assign.cpp57 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
58 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
Daco_ir.cpp186 if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) in can_use_SDWA()
194 if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) in can_use_SDWA()
274 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8) in convert_to_SDWA()
Daco_lower_to_hw_instr.cpp407 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
445 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
447 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
783 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) { in emit_reduction()
796 if (dst.regClass().type() == RegType::sgpr) { in emit_reduction()
834 assert(input_data.regClass().type() == RegType::vgpr); in emit_gfx10_wave64_bpermute()
894 assert(input.regClass().type() == RegType::vgpr); in emit_gfx6_bpermute()
934 max_size = MIN2(max_size, src.def.regClass().type() == RegType::vgpr ? 4 : 8); in split_copy()
1094 … Definition lo_half = Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte())); in do_copy()
1095 … Definition dst = Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes())); in do_copy()
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Daco_optimizer.cpp535 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr)) in can_swap_operands()
698 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) { in check_vop3_operands()
858 if (info.is_temp() && info.temp.type() == RegType::sgpr) { in label_instruction()
861 } else if (info.is_temp() && info.temp.type() == RegType::vgpr && in label_instruction()
871 … [] (const Definition& def) { return def.getTemp().type() != RegType::vgpr;}); in label_instruction()
892 … if (info.is_temp() && info.temp.type() == RegType::vgpr && valu_can_accept_vgpr(instr, i)) { in label_instruction()
897 …if (info.is_temp() && info.temp.type() == RegType::sgpr && can_apply_sgprs(ctx, instr) && instr->o… in label_instruction()
1108 bool accept_subdword = instr->definitions[0].regClass().type() == RegType::vgpr && in label_instruction()
1111 …ctx.program->chip_class >= GFX9 || (op.hasRegClass() && op.regClass().type() == RegType::vgpr));}); in label_instruction()
1127 (!op.hasRegClass() || op.regClass().type() == RegType::sgpr))) in label_instruction()
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Daco_register_allocation.cpp102 if (rc.type() == RegType::vgpr) { in DefInfo()
539 if (rc.type() == RegType::vgpr) { in adjust_max_used_regs()
1151 if (rc.type() == RegType::vgpr) { in get_reg_specified()
1270 if (info.rc.type() == RegType::vgpr && ctx.program->max_reg_demand.vgpr < max_addressible_vgpr) { in get_reg()
1273 …} else if (info.rc.type() == RegType::sgpr && ctx.program->max_reg_demand.sgpr < max_addressible_s… in get_reg()
1296 if (rc.type() == RegType::vgpr) { in get_reg_create_vector()
1456 if (def.getTemp().type() == RegType::sgpr) { in handle_pseudo()
1465 if (op.isTemp() && op.getTemp().type() == RegType::sgpr) { in handle_pseudo()
2017 phi->operands[idx].getTemp().type() == RegType::sgpr && in register_allocation()
2078 instr->operands[2].getTemp().type() == RegType::vgpr && in register_allocation()
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Daco_insert_NOPs.cpp370 if (def.regClass().type() != RegType::sgpr) { in handle_instruction_gfx6()
400 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr) in handle_instruction_gfx6()
462 if (def.regClass().type() == RegType::sgpr) { in handle_instruction_gfx6()
500 instr->operands[1].regClass().type() == RegType::vgpr && in handle_instruction_gfx6()
564 return def.getTemp().type() == RegType::sgpr; in instr_writes_sgpr()
Daco_lower_phis.cpp267 assert(phi_src.regClass().type() == RegType::sgpr); in lower_subdword_phis()
268 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size())); in lower_subdword_phis()
Daco_live_var_analysis.cpp246 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) in process_live_temps_per_block()
Daco_assembler.cpp454 } else if (instr->operands[1].regClass().type() == RegType::vgpr) { in emit_instruction()
458 if (instr->operands[1].regClass().type() == RegType::sgpr) in emit_instruction()
Daco_insert_waitcnt.cpp834 instr->operands[1].regClass().type() == RegType::vgpr) { in gen()
Daco_insert_exec_mask.cpp114 if (def.getTemp().type() == RegType::vgpr) in pred_by_exec_mask()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerX86Base.h757 template <typename RegType, typename RmType>
758 inline void emitXmmRegisterOperand(RegType reg, RmType rm);
812 template <typename RegType, typename T = Traits>
814 gprEncoding(const RegType Reg) { in gprEncoding()
818 template <typename RegType, typename T = Traits>
820 gprEncoding(const RegType Reg) { in gprEncoding()
824 template <typename RegType>
825 bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) { in is8BitRegisterRequiringRex()
827 std::is_same<typename std::decay<RegType>::type, ByteRegister>::value || in is8BitRegisterRequiringRex()
828 std::is_same<typename std::decay<RegType>::type, GPRRegister>::value; in is8BitRegisterRequiringRex()
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DIceTargetLoweringMIPS32.cpp1643 Type RegType; in addProlog() local
1645 RegType = IceType_f32; in addProlog()
1647 RegType = IceType_i32; in addProlog()
1648 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1649 StackOffset -= typeWidthInBytesOnStack(RegType); in addProlog()
1652 Func, RegType, SP, in addProlog()
1767 Type RegType; in addEpilog() local
1769 RegType = IceType_f32; in addEpilog()
1771 RegType = IceType_i32; in addEpilog()
1772 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
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/external/mesa3d/src/amd/compiler/tests/
Dhelpers.cpp112 …RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0'… in setup_cs()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5583 string kind2, RegisterOperand RegType,
5586 BaseSIMDThreeSameVectorTied<Q, U, 0b100, {0b1001, Mixed}, RegType, asm, kind1,
5587 [(set (AccumType RegType:$dst),
5588 (OpNode (AccumType RegType:$Rd),
5589 (InputType RegType:$Rn),
5590 (InputType RegType:$Rm)))]> {
5605 string kind2, RegisterOperand RegType,
5608 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5609 [(set (AccumType RegType:$dst),
5610 (OpNode (AccumType RegType:$Rd),
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5406 string kind2, RegisterOperand RegType,
5409 BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
5410 [(set (AccumType RegType:$dst),
5411 (OpNode (AccumType RegType:$Rd),
5412 (InputType RegType:$Rn),
5413 (InputType RegType:$Rm)))]> {
5428 string kind2, RegisterOperand RegType,
5431 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
5432 [(set (AccumType RegType:$dst),
5433 (OpNode (AccumType RegType:$Rd),
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DAArch64FrameLowering.cpp1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV5.td907 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
915 let Inst{27-24} = RegType;
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp4779 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
4780 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCodeGenPrepare.cpp6350 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
6351 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()

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