| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 241 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
243 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
248 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 247 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
249 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
254 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 254 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
256 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1104 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1105 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
1106 RegVT == MVT::i32 || RegVT == MVT::f32) { in LowerFormalArguments()
1110 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1111 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { in LowerFormalArguments()
1115 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1118 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1123 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1125 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
175 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
178 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 229 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
230 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
234 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /external/llvm-project/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 262 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
263 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
267 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
275 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
280 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
283 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | SwitchLoweringUtils.h | 213 MVT RegVT; member
227 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SwitchLoweringUtils.h | 208 MVT RegVT; member
222 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 1045 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1047 if (RegVT == MVT::i8) { in LowerFormalArguments()
1049 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1056 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1073 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1078 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1177 EVT RegVT = VA.getLocVT(); in LowerCall() local
1187 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1190 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1193 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 1070 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1072 if (RegVT == MVT::i8) { in LowerFormalArguments()
1074 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1081 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1098 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1199 EVT RegVT = VA.getLocVT(); in LowerCall() local
1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1215 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 485 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
486 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
489 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
495 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 484 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
485 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
494 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
437 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
442 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 444 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
445 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
469 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 643 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
644 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
649 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
643 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
648 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 3207 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
3208 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
3275 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
3277 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
3281 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
3296 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, in expandUnalignedLoad()
3315 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
3432 MVT RegVT = in expandUnalignedStore() local
3438 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
3442 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in expandUnalignedStore()
[all …]
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| D | SelectionDAGBuilder.h | 291 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
297 MVT RegVT; member
|
| D | SelectionDAGBuilder.cpp | 2170 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2171 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2200 MVT VT = BB.RegVT; in visitBitTestCase()
6486 MVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue() local
6487 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) { in GetRegistersForValue()
6489 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
6490 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
6491 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
6496 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); in GetRegistersForValue()
6498 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 788 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
790 RegVT = VA.getValVT(); in LowerFormalArguments()
792 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
794 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
800 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
801 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
802 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
803 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
807 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
809 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 818 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
820 RegVT = VA.getValVT(); in LowerFormalArguments()
822 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
824 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
830 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
831 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
832 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
833 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
837 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
839 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3080 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3082 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3087 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3093 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3094 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3095 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3097 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3101 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
|