Searched refs:RegVTs (Results 1 – 8 of 8) sorted by relevance
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 836 SmallVector<MVT, 4> RegVTs; member
864 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); in append()
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| D | SelectionDAGBuilder.cpp | 761 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), in RegsForValue()
782 RegVTs.push_back(RegisterVT); in RegsForValue()
807 CallConv.getValue(), RegVTs[Value]) in getCopyFromRegs()
808 : RegVTs[Value]; in getCopyFromRegs()
890 CallConv.getValue(), RegVTs[Value]) in getCopyToRegs()
891 : RegVTs[Value]; in getCopyToRegs()
958 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && in AddInlineAsmOperands()
963 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); in AddInlineAsmOperands()
974 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands()
987 for (auto CountAndVT : zip_first(RegCount, RegVTs)) { in getRegsAndSizes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 845 SmallVector<MVT, 4> RegVTs; member
873 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); in append()
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| D | SelectionDAGBuilder.cpp | 776 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), in RegsForValue()
797 RegVTs.push_back(RegisterVT); in RegsForValue()
822 CallConv.getValue(), RegVTs[Value]) in getCopyFromRegs()
823 : RegVTs[Value]; in getCopyFromRegs()
905 CallConv.getValue(), RegVTs[Value]) in getCopyToRegs()
906 : RegVTs[Value]; in getCopyToRegs()
973 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && in AddInlineAsmOperands()
978 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); in AddInlineAsmOperands()
989 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands()
1002 for (auto CountAndVT : zip_first(RegCount, RegVTs)) { in getRegsAndSizes()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 970 SmallVector<MVT, 4> RegVTs; member
988 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); in append()
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| D | SelectionDAGBuilder.cpp | 620 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} in RegsForValue()
631 RegVTs.push_back(RegisterVT); in RegsForValue()
657 MVT RegisterVT = RegVTs[Value]; in getCopyFromRegs()
758 MVT RegisterVT = RegVTs[Value]; in getCopyToRegs()
828 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands()
6903 MatchedRegs.RegVTs.push_back(RegVT); in visitInlineAsm()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 463 const std::vector<ValueTypeByHwMode> &RegVTs = in HasOneImplicitDefWithKnownVT() local
465 if (RegVTs.size() == 1 && RegVTs[0].isSimple()) in HasOneImplicitDefWithKnownVT()
466 return RegVTs[0].getSimple().SimpleTy; in HasOneImplicitDefWithKnownVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 376 const std::vector<MVT::SimpleValueType> &RegVTs = in HasOneImplicitDefWithKnownVT() local
378 if (RegVTs.size() == 1) in HasOneImplicitDefWithKnownVT()
379 return RegVTs[0]; in HasOneImplicitDefWithKnownVT()
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