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Searched refs:RegisterSize (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp1005 unsigned RegisterSize = RegisterVT.getSizeInBits(); in getRegsAndSizes() local
1007 OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); in getRegsAndSizes()
1364 unsigned RegisterSize = RegAndSize.second; in handleDebugValue() local
1368 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) in handleDebugValue()
1370 : RegisterSize; in handleDebugValue()
1378 Offset += RegisterSize; in handleDebugValue()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp990 TypeSize RegisterSize = RegisterVT.getSizeInBits(); in getRegsAndSizes() local
992 OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); in getRegsAndSizes()
1324 unsigned RegisterSize = RegAndSize.second; in handleDebugValue() local
1328 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) in handleDebugValue()
1330 : RegisterSize; in handleDebugValue()
1338 Offset += RegisterSize; in handleDebugValue()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp783 unsigned RegisterSize = DAG.getTargetLoweringInfo() in shouldTransformMulToShiftsAddsSubs() local
786 Steps *= (VT.getSizeInBits() != RegisterSize) * 3; in shouldTransformMulToShiftsAddsSubs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp783 unsigned RegisterSize = DAG.getTargetLoweringInfo() in shouldTransformMulToShiftsAddsSubs() local
786 Steps *= (VT.getSizeInBits() != RegisterSize) * 3; in shouldTransformMulToShiftsAddsSubs()