| /external/llvm-project/llvm/test/TableGen/ |
| D | AsmPredicateCombiningRISCV.td | 23 def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
28 let InOperandList = (ins Regs:$r);
38 let InOperandList = (ins Regs:$r);
67 def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
73 def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
80 def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
86 def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
94 def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
333 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
334 if (!isAllocated(Regs[i])) in getFirstUnallocated()
336 return Regs.size(); in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
360 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
361 if (FirstUnalloc == Regs.size()) in AllocateReg()
365 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
374 if (RegsRequired > Regs.size()) in AllocateRegBlock()
[all …]
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| D | RegisterPressure.h | 258 RegSet Regs;
279 RegSet::const_iterator I = Regs.find(SparseIndex);
280 if (I == Regs.end())
289 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
302 RegSet::iterator I = Regs.find(SparseIndex);
303 if (I == Regs.end())
311 return Regs.size();
316 for (const IndexMaskPair &P : Regs) {
398 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
337 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
338 if (!isAllocated(Regs[i])) in getFirstUnallocated()
340 return Regs.size(); in getFirstUnallocated()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
371 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
372 if (FirstUnalloc == Regs.size()) in AllocateReg()
376 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
385 if (RegsRequired > Regs.size()) in AllocateRegBlock()
[all …]
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| D | RegisterPressure.h | 275 RegSet Regs; variable
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
298 if (I == Regs.end()) in contains()
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
321 if (I == Regs.end()) in erase()
329 return Regs.size(); in size()
334 for (const IndexMaskPair &P : Regs) { in appendTo()
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
345 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
346 if (!isAllocated(Regs[i])) in getFirstUnallocated()
348 return Regs.size(); in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
372 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
373 if (FirstUnalloc == Regs.size()) in AllocateReg()
377 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
386 if (RegsRequired > Regs.size()) in AllocateRegBlock()
[all …]
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| D | RegisterPressure.h | 275 RegSet Regs; variable
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
298 if (I == Regs.end()) in contains()
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
321 if (I == Regs.end()) in erase()
329 return Regs.size(); in size()
334 for (const IndexMaskPair &P : Regs) { in appendTo()
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 39 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass() argument
42 RegNo = Regs[RegNo]; in decodeRegisterClass()
258 const unsigned *Regs) in decodeBDAddr12Operand() argument
264 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDAddr12Operand()
271 const unsigned *Regs) in decodeBDAddr20Operand() argument
277 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDAddr20Operand()
283 const unsigned *Regs) in decodeBDXAddr12Operand() argument
290 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); in decodeBDXAddr12Operand()
292 MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); in decodeBDXAddr12Operand()
298 const unsigned *Regs) in decodeBDXAddr20Operand() argument
[all …]
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| /external/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
85 RegNo = Regs[RegNo]; in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand() argument
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand() argument
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
85 RegNo = Regs[RegNo]; in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand() argument
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand() argument
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
[all …]
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 46 SmallVector<Register, 4> Regs; member
55 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
58 : Regs(Regs.begin(), Regs.end()), Ty(Ty),
60 if (!Regs.empty() && Flags.empty())
64 (Regs.empty() || Regs[0] == 0)) &&
152 assert(Arg.Regs.size() == 1); in assignValueToAddress()
153 assignValueToAddress(Arg.Regs[0], Addr, Size, MPO, VA); in assignValueToAddress()
|
| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 72 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
75 const std::deque<CodeGenRegister> &Regs,
200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
201 if (Regs.empty()) in EmitRegUnitPressure()
206 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
345 for (auto &RE : Regs) { in EmitRegMappingTables()
364 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
412 for (auto &RE : Regs) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
[all …]
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
80 RegNo = Regs[RegNo]; in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand() argument
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand() argument
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
296 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | InlineAsmLowering.cpp | 40 SmallVector<Register, 1> Regs; member in __anonda11b35f0111::GISelAsmOperandInfo
137 OpInfo.Regs.push_back(R); in getRegistersForValue()
399 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
410 OpInfo.Regs.size()); in lowerInlineAsm()
411 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); in lowerInlineAsm()
422 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
545 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
552 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm()
565 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 47 SmallVector<Register, 4> Regs; member
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
59 : Regs(Regs.begin(), Regs.end()), Ty(Ty),
61 if (!Regs.empty() && Flags.empty())
64 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) &&
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 64 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); in splitToValueTypes()
74 SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), in splitToValueTypes()
89 SplitRegs.push_back(Info.Regs[0]); in splitToValueTypes()
212 [&](ArrayRef<Register> Regs) { in lowerReturn() argument
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments() argument
358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
414 if (OrigArg.Regs.size() > 1) in lowerCall()
418 [&](ArrayRef<Register> Regs) { in lowerCall() argument
419 MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]); in lowerCall()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 64 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); in splitToValueTypes()
74 SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), in splitToValueTypes()
89 SplitRegs.push_back(Info.Regs[0]); in splitToValueTypes()
212 [&](ArrayRef<Register> Regs) { in lowerReturn() argument
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
354 [&](ArrayRef<Register> Regs) { in lowerFormalArguments() argument
355 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
411 if (OrigArg.Regs.size() > 1) in lowerCall()
415 [&](ArrayRef<Register> Regs) { in lowerCall() argument
416 MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]); in lowerCall()
[all …]
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
89 const std::deque<CodeGenRegister> &Regs,
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
385 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
391 for (auto &RE : Regs) { in EmitRegMappingTables()
409 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
457 for (auto &RE : Regs) { in EmitRegMappingTables()
520 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
524 for (auto &RE : Regs) { in EmitRegMapping()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 228 Args[i].OrigRegs.push_back(Args[i].Regs[0]); in handleAssignments()
229 Args[i].Regs.clear(); in handleAssignments()
246 Args[i].Regs.push_back(Reg); in handleAssignments()
262 Register LargeReg = Args[i].Regs[0]; in handleAssignments()
268 Args[i].Regs.clear(); in handleAssignments()
279 Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); in handleAssignments()
301 Register ArgReg = Args[i].Regs[0]; in handleAssignments()
309 unsigned NumArgRegs = Args[i].Regs.size(); in handleAssignments()
318 Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA); in handleAssignments()
323 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); in handleAssignments()
[all …]
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| /external/perfetto/src/profiling/perf/ |
| D | regs_parsing.cc | 118 std::unique_ptr<unwindstack::Regs> ToLibUnwindstackRegs( in ToLibUnwindstackRegs()
137 return std::unique_ptr<unwindstack::Regs>( in ToLibUnwindstackRegs()
154 return std::unique_ptr<unwindstack::Regs>( in ToLibUnwindstackRegs()
179 return std::unique_ptr<unwindstack::Regs>( in ToLibUnwindstackRegs()
196 return std::unique_ptr<unwindstack::Regs>( in ToLibUnwindstackRegs()
211 std::unique_ptr<unwindstack::Regs> ReadPerfUserRegsData(const char** data) { in ReadPerfUserRegsData()
212 unwindstack::ArchEnum requested_arch = unwindstack::Regs::CurrentArch(); in ReadPerfUserRegsData()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.cpp | 106 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
107 while (Regs) { in EmitVFPRegSave()
109 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
110 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
120 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
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| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.cpp | 107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
108 while (Regs) { in EmitVFPRegSave()
110 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
121 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.cpp | 107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
108 while (Regs) { in EmitVFPRegSave()
110 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
121 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
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| /external/llvm-project/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
97 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
97 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
|