| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 156 BitVector RegsUsed; member in __anon8074828c0111::GCNRegBankReassign
320 if (RegsUsed.test(Reg + I)) in getRegBankMask()
322 RegsUsed.set(Reg, Reg + Size); in getRegBankMask()
331 if (Reg + StartBit >= RegsUsed.size()) in getRegBankMask()
339 if (RegsUsed.test(StartBit + Reg + I)) in getRegBankMask()
341 RegsUsed.set(StartBit + Reg, StartBit + Reg + Size); in getRegBankMask()
360 RegsUsed.reset(); in analyzeInst()
749 RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() + in runOnMachineFunction()
798 RegsUsed.clear(); in runOnMachineFunction()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 175 BitVector RegsUsed; member in __anondebd7f180111::GCNRegBankReassign
361 if (RegsUsed.test(RegNo + I)) in getRegBankMask()
363 RegsUsed.set(RegNo, RegNo + Size); in getRegBankMask()
372 if (RegNo + StartBit >= RegsUsed.size()) in getRegBankMask()
380 if (RegsUsed.test(StartBit + RegNo + I)) in getRegBankMask()
382 RegsUsed.set(StartBit + RegNo, StartBit + RegNo + Size); in getRegBankMask()
400 RegsUsed.reset(); in analyzeInst()
825 RegsUsed.resize(NumRegBanks); in runOnMachineFunction()
865 RegsUsed.clear(); in runOnMachineFunction()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 766 VarList &SortedSpilledVariables, SmallBitVector &RegsUsed, in getVarStackSlotParams() argument
808 RegsUsed[Var->getRegNum()] = true; in getVarStackSlotParams()
|
| D | IceTargetLowering.h | 457 SmallBitVector &RegsUsed, size_t *GlobalsSize,
|
| D | IceTargetLoweringMIPS32.cpp | 1517 RegsUsed = SmallBitVector(CalleeSaves.size()); in addProlog()
1542 getVarStackSlotParams(SortedSpilledVariables, RegsUsed, &GlobalsSize, in addProlog()
1552 if (RegsUsed[RegMIPS32::Reg_FP]) { in addProlog()
1556 RegsUsed[RegMIPS32::Reg_FP] = true; in addProlog()
1560 RegsUsed[RegMIPS32::Reg_RA] = true; in addProlog()
1568 if (CalleeSaves[i] && RegsUsed[i]) { in addProlog()
|
| D | IceTargetLoweringARM32.cpp | 1471 RegsUsed = SmallBitVector(CalleeSaves.size()); in addProlog()
1494 getVarStackSlotParams(SortedSpilledVariables, RegsUsed, &GlobalsSize, in addProlog()
1512 if (RegsUsed[RegARM32::Reg_fp]) { in addProlog()
1516 RegsUsed[RegARM32::Reg_fp] = true; in addProlog()
1520 RegsUsed[RegARM32::Reg_lr] = true; in addProlog()
1533 if (CalleeSaves[i] && RegsUsed[i]) { in addProlog()
|
| D | IceTargetLoweringMIPS32.h | 845 SmallBitVector RegsUsed; variable
|
| D | IceTargetLoweringARM32.h | 1234 SmallBitVector RegsUsed; variable
|
| D | IceTargetLoweringX86BaseImpl.h | 1064 RegsUsed = SmallBitVector(CalleeSaves.size());
1092 getVarStackSlotParams(SortedSpilledVariables, RegsUsed, &GlobalsSize,
1105 if (RegsUsed[i]) {
1126 (RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None)).count() ==
1403 if (CalleeSaves[i] && RegsUsed[i]) {
|
| D | IceTargetLoweringX86Base.h | 1096 SmallBitVector RegsUsed; variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 4043 SmallSet<unsigned, 8> RegsUsed; in LowerCall() local
4111 if (RegsUsed.count(VA.getLocReg())) { in LowerCall()
4133 RegsUsed.insert(VA.getLocReg()); in LowerCall()
4371 SmallSet<unsigned, 4> RegsUsed; in LowerReturn() local
4405 if (RegsUsed.count(VA.getLocReg())) { in LowerReturn()
4415 RegsUsed.insert(VA.getLocReg()); in LowerReturn()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5230 SmallSet<unsigned, 8> RegsUsed; in LowerCall() local
5343 if (RegsUsed.count(VA.getLocReg())) { in LowerCall()
5365 RegsUsed.insert(VA.getLocReg()); in LowerCall()
5590 SmallSet<unsigned, 4> RegsUsed; in LowerReturn() local
5624 if (RegsUsed.count(VA.getLocReg())) { in LowerReturn()
5634 RegsUsed.insert(VA.getLocReg()); in LowerReturn()
|